在imx6q中到最后调用rt_system_scheduler_start总会出现undefined abort

发表在 Kernel2019-4-24 12:01 [复制链接] 6 418

  1. void rt_system_scheduler_start(void)
    ) ^" G5 \+ ?9 t6 z3 _. H$ M! C+ j
  2. {& [/ l- \) ~. o  S- X# [1 g1 f
  3.     register struct rt_thread *to_thread;
    9 e/ V8 T# N: |- @0 G
  4.     rt_ubase_t highest_ready_priority;
    6 @+ ]1 z; K; K

  5.   U- D+ A; W8 a+ I: D
  6.     to_thread = _get_highest_priority_thread(&highest_ready_priority);6 W* @( ]# C  q2 q- m3 m5 E

  7. 1 o% o5 J! x2 f0 R" {
  8. #ifdef RT_USING_SMP
    7 y% m$ d- U# k- U
  9.     to_thread->oncpu = rt_hw_cpu_id();
    . i$ W% S# X, V: f! {
  10. #else* o* N" l. d/ P- R3 P7 H
  11.     rt_current_thread = to_thread;' }# p7 _9 A- T
  12. #endif /*RT_USING_SMP*/; D; S8 f3 W1 A) U; g7 o" c+ l

  13. . z# S; N. ?! N$ ~& s2 D- Y) j& Q
  14.     rt_schedule_remove_thread(to_thread);
    5 a; G. M0 d3 b7 a
  15.     to_thread->stat = RT_THREAD_RUNNING;
    / G5 H& Z) _3 @% q+ v! q

  16. ! l0 E9 I, _4 `+ ]8 Y4 h% \4 \# i- _
  17.     /* switch to new thread */% A# ?: i+ F% c8 ~/ [) K5 ~+ U2 ^
  18. #ifdef RT_USING_SMP9 n  a/ V- ?/ g8 i! f; j
  19.     rt_hw_context_switch_to((rt_ubase_t)&to_thread->sp, to_thread);
    ; f6 }2 \% }/ v
  20. #else& x% J; Y: f/ X" }! m  G
  21.     rt_hw_context_switch_to((rt_ubase_t)&to_thread->sp);
    7 a5 K! q! v% V$ ~
  22. #endif /*RT_USING_SMP*/( N8 K. W4 h8 P
  23. % h! r& V' k; y8 O! V9 {+ Y- r
  24.     /* never come back */% s/ ~$ Z4 `. B" w; U. G- _
  25. }
复制代码
#ifdef RT_USING_SMP% a6 N- I9 N" Z1 D
    rt_hw_context_switch_to((rt_ubase_t)&to_thread->sp, to_thread);( u2 U: O0 r0 b  `2 ]
#else
5 n* b& x) p: H9 Y, ]* Q) \    rt_hw_context_switch_to((rt_ubase_t)&to_thread->sp);
/ X, G/ @8 Y* U2 |7 \: c
, j/ R' ^7 v, @5 H3 E用IAR DEBUG时,打断点发现每次一到这最后一句然后跳转到初始化过的  thread时,总会出现异常指令退出,rt_hw_context_switch_to 定义位于context.s参考的是qemu_vexpress_a9中的例子context_gcc.S,都是多核按理说这个应该是一致的,无须修改。
3 S4 s0 ~8 ^+ S* }# M; q9 _下面给出修改过的适用于IAR的汇编文件context.s
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  1.         PUBLIC rt_hw_context_switch_interrupt$ `* o: X7 Y' {* G
  2.         PUBLIC rt_hw_context_switch1 t% f$ S2 ^: I, `
  3.         PUBLIC rt_hw_context_switch_to
    ; J3 h5 D4 e: ]; `+ @" b
  4. ;        PUBLIC rt_hw_interrupt_enable
    8 b- L3 i) z0 G8 y; T" }
  5. ;        PUBLIC rt_hw_interrupt_disable' _+ E( u& v: Y# V

  6. * b' p3 b6 n3 D) o8 t

  7. # r, }: `, O+ c/ `- p
  8.     SECTION .text:CODE:ROOT(2)% Y; z5 B# e/ E  z# j
  9.         ARM
    % K* e# K$ J% |! B7 O( E" U
  10.         IMPORT  rt_cpus_lock_status_restore
    % f6 e. q9 j* N6 j9 M. \5 F
  11.         IMPORT rt_interrupt_to_thread! {! W; {3 [# t' @3 P, w  K8 c4 u7 X* e
  12.         IMPORT rt_thread_switch_interrupt_flag2 G: \, o0 t# U
  13.         IMPORT rt_interrupt_from_thread3 @% |0 S7 \9 g% b/ [
  14. #include "rtconfig.h"8 a$ |9 w; O& u3 i  J; Y3 V0 F+ R
  15. - H1 \) Q; ]: W0 H1 S
  16. #ifdef RT_USING_SMP' o' o; A! s9 u
  17.         PUBLIC rt_hw_local_irq_enable# u* `! X. }  T3 W
  18.         PUBLIC rt_hw_local_irq_disable
    / v) P5 X- _* ^& o/ A0 d
  19. ; rt_base_t rt_hw_interrupt_disable();7 b/ K5 }4 B9 @/ E/ m; D( m. o

  20. ! k' _% k# V! @2 k
  21. rt_hw_local_irq_disable:" i, m: f' C# a5 o% X/ t9 w" y
  22.     mrs r0, cpsr
    % v$ b3 \& p5 l& U3 L
  23.     cpsid i
    0 g: U. s2 h: R, \
  24.     bx  lr  a  N4 c  A+ ]8 s8 y
  25. ( V7 [+ Q- d9 Y5 Z
  26. ;void rt_hw_interrupt_enable(rt_base_t level);+ R) z3 v' k' }  P# y

  27. $ ^0 U3 V1 J$ F1 f0 o
  28. # a* H" O) e! t( T/ a' Y7 Y
  29. rt_hw_local_irq_enable:7 A7 G* b9 g8 Y' a8 J
  30.     msr cpsr, r0
    & @2 ?9 o* ?; X! c; b
  31.     bx  lr
    6 o) O/ [6 {$ D

  32. - E1 A5 J' x! M2 {! Q; [. ]1 A9 M
  33. #else
    ) a6 v. ]5 m" Q- p
  34.         PUBLIC rt_hw_interrupt_disable
    5 M  }) U( B  f7 M$ a
  35.         PUBLIC rt_hw_interrupt_enable
    ) @6 @& H4 j9 v3 W# X) v

  36. 8 }+ }# O; ~- V. m; Z
  37. ; rt_base_t rt_hw_interrupt_disable();8 I9 W3 `) W0 b1 ~7 [

  38. ) c$ H5 X: V. z( h: A" A2 b
  39. rt_hw_interrupt_disable:
    0 P' z& j/ W. l) Q: g( H1 s
  40.     mrs r0, cpsr
    ; X3 @/ H+ V7 I! ^
  41.     cpsid i
    ; A# V7 S& ^7 d0 x  U4 `# [% X
  42.     bx  lr2 l. w  J2 R5 |  w4 H
  43. 0 f+ S1 P  ~/ P$ T
  44. 2 j" K6 e3 Y- U0 x  u
  45. ; void rt_hw_interrupt_enable(rt_base_t level);
    - y: X' W5 {+ u% Y

  46. 6 l, S6 N$ A, n: W
  47. ) l4 F) E" l+ I5 O$ z
  48. rt_hw_interrupt_enable:
    1 n  J3 R/ s  W3 r' q. j
  49.     msr cpsr, r0
    # D' V+ {5 l3 J! o
  50.     bx  lr( F6 Z$ h* e, A% d
  51. % J) x/ D$ Q- ]' }8 D$ d

  52. 7 F* Z! Z, T0 E' V7 @- h# B
  53. #endif4 ^6 }3 A- }; h1 N

  54. ' t3 o, c; [. i* k& D* C2 |
  55. . \; Q+ Q/ E4 ?: k8 M, v) C
  56. ; void rt_hw_context_switch_to(rt_ubase_t to, struct rt_thread *to_thread);* U$ N8 g( j7 C3 b5 d+ B. A- M2 m
  57. ; r0 --> to& u* a0 G) {  t) K% r/ f

  58. : ?$ m& h7 k% |, {( X, `3 Y* b. }) \

  59. " ^! V/ U: Z0 r& @
  60. rt_hw_context_switch_to:
    / Q3 W1 |6 P0 o
  61.     ldr sp, [r0]            ; get new task stack pointer
    2 e9 p0 q6 F8 L# P6 s
  62. ' o, m& U+ u% `9 O3 w
  63. #ifdef RT_USING_SMP9 L8 ~7 A/ E! s& z8 l
  64.     mov     r0, r1
    / W) p0 _/ o; Z" A: P. d2 u# u" l
  65.     bl      rt_cpus_lock_status_restore' d1 e% ^* o; W% v- Z
  66. #endif7 I' @, k% \. A3 U' }3 M$ E) |" ]
  67. ;/*RT_USING_SMP*/
      L$ h+ ?9 Y/ n( _
  68.   Z* c6 P, A& x, C
  69. #ifdef RT_USING_LWP8 r4 C# r1 x2 r' s, a0 O
  70.     ldmfd sp, {r13, r14}^   ; pop usr_sp usr_lr  m% a- r9 q, d+ @/ Y. g
  71.     add sp, #8* K1 w$ ^( @1 y
  72. #endif2 ^% c& Q' T3 \. e" l+ X
  73. 7 ]# @& S& w% H# h7 V( T
  74.     ldmfd sp!, {r4}         ; pop new task spsr) H" D* F! K7 H( F# B
  75.     msr spsr_cxsf, r4$ k9 A: u2 A& D- W* g5 c# h% y& [

  76. 2 W' d! b( v) L% B  G
  77.     ldmfd sp!, {r0-r12, lr, pc}^   ; pop new task r0-r12, lr & pc4 `% w. e7 L/ U  R  E! B
  78. " G) B4 _1 B4 f
  79. ;.section .bss.share.isr' `3 P- Z( m$ e$ [3 d3 N, v
  80. ;_guest_switch_lvl:$ [9 R. X$ W0 S1 v: B) C' ^
  81. ;   DCD 0  ]9 k& j: `7 r+ _/ i3 f

  82. 0 D# I8 ~* D; g7 G  ]/ Y. j2 J
  83. ;.section .text.isr, "ax"
    3 i, [) B. O; \) t5 C
  84. 4 d- O, T$ f3 i
  85. $ X& }6 P3 w  g$ C% h; ^4 E% Q9 M
  86. ; void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);: K( \6 D( ?; [+ b$ `( P
  87. ; r0 --> from% S0 f' I9 E) S, o' Q2 r6 ?: p* [
  88. ; r1 --> to3 a$ D& f# Y- U% U/ ^& R

  89. ; J0 Q* |# z. R4 t! G8 I

  90. ; J! W2 J4 f' C( U. M2 ~
  91. rt_hw_context_switch:
    ! V9 _' N7 A: N9 h+ I. U% T
  92.     stmfd   sp!, {lr}       ; push pc (lr should be pushed in place of PC)+ ]0 j. |0 L0 ^
  93.     stmfd   sp!, {r0-r12, lr}   ; push lr & register file
    * ~4 G. h9 d) ~! I6 {9 Z6 B) P2 w

  94. ) q' B8 B1 b$ `, R7 J
  95.     mrs r4, cpsr$ z+ {' E- Q: u/ P# f) Q
  96.     tst lr, #0x01/ G4 |& n, v- G3 s- G4 y- h
  97.     orrne r4, r4, #0x20     ; it's thumb code
    " c3 ?, L7 V' e2 Y' W1 v

  98. ( X" W3 Y/ Q! K5 ?( j' G; Y) o' `& f
  99.     stmfd sp!, {r4}         ; push cpsr
      p9 S+ c6 x# k9 V/ Y$ f

  100.   c+ \$ U7 j. {+ }$ X
  101. #ifdef RT_USING_LWP
    4 e% a; F2 \" R# |
  102.     stmfd sp, {r13, r14}^   ; push usr_sp usr_lr8 ?% E# g1 ?) b8 c7 b, h' P
  103.     sub sp, #8
    ' ^  j2 T/ [, i% i- `
  104. #endif
    & u% l% T5 I4 n# c8 @5 K

  105. ) A: y1 p6 \" ~+ E: u1 X
  106.     str sp, [r0]            ; store sp in preempted tasks TCB
    - d; f8 A2 ^; Y, C
  107.     ldr sp, [r1]            ; get new task stack pointer
    4 j9 m8 H) y/ P% @

  108. 0 {* Q# W% d$ h! q6 r3 ?
  109. #ifdef RT_USING_SMP8 d$ S6 `1 m2 R
  110.     mov     r0, r2
    # y, B& G% ^* l9 G  m
  111.     bl      rt_cpus_lock_status_restore( [7 `3 S1 R' @0 V! P
  112. #endif
    3 R( A, A5 H- b2 b( @
  113. ;/*RT_USING_SMP*/
    , E; S" Z8 C% N- p7 Y% h& ~

  114. . _1 l6 M2 o! o+ a+ H1 h$ P' a
  115. #ifdef RT_USING_LWP/ Z" q% {# R/ x+ p6 ?
  116.     ldmfd sp, {r13, r14}^   ; pop usr_sp usr_lr1 e6 ]- r: w/ g! s: R1 D
  117.     add sp, #8+ W0 d/ h& Z6 G( V* M$ n+ M
  118. #endif+ e2 Y' j' e7 o/ c' h

  119. 7 e4 ~5 k% k7 p/ z- a2 H
  120.     ldmfd sp!, {r4}         ; pop new task cpsr to spsr
    ; O' D' I2 ^7 }& t1 V6 K
  121.     msr spsr_cxsf, r4% ^8 J0 y8 ^8 u# y( w
  122.     ldmfd sp!, {r0-r12, lr, pc}^  ; pop new task r0-r12, lr & pc, copy spsr to cpsr
    3 O! f, X/ {/ l

  123. 4 ?( S+ V! f3 J; w
  124. ; g8 V  `5 K4 s( ^3 N" }. r3 L
  125.         #define Mode_USR        0x107 j/ {5 b, @3 M& j7 q; ^
  126.         #define Mode_FIQ        0x11* s$ T0 L: C# w, X2 I2 R& ^
  127.         #define Mode_IRQ        0x124 t* u0 A* z4 k
  128.         #define Mode_SVC        0x13' \- E8 X. Z# f: F" j5 ~% G7 L  Q
  129.         #define Mode_ABT        0x17
    7 l$ J( O0 I- X. @# d. I( j- o# M
  130.         #define Mode_UND        0x1B
    3 |9 {4 L0 x/ m  `/ A, }" V
  131.         #define Mode_SYS        0x1F
    . g0 `  ]8 d; A& {6 E7 D: z
  132. ; ~9 o3 Q9 D5 }8 ]% C' @
  133.         #define I_Bit           0x80
    4 e$ M& Y& N/ y5 E9 @
  134.         ; when I bit is set, IRQ is disabled% F, I6 I: X% z0 X/ B" Q
  135.         #define        F_Bit           0x405 C) m0 z6 x# _1 W. _: a
  136.         ; when F bit is set, FIQ is disabled! w) d' ~1 E8 M3 K& G0 S9 {, @" M
  137. 7 P1 J) G; a" e" R. x
  138. ) _  @' z7 \1 e( j' k: a( w( w
  139. ; void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
    " `7 q) f9 K  d2 a/ D
  140. % f6 a$ t2 G  e6 \. V4 W, }

  141.   `+ `/ A- ]7 f& {3 S3 |" ?- V
  142. 1 h$ m3 y6 |1 C* F/ ]1 O
  143. rt_hw_context_switch_interrupt:
    5 X" H2 u- H( j) {4 y% Z- _
  144. #ifdef RT_USING_SMP; v2 P0 Z9 D! Y  n0 h7 j! @1 y
  145.     ; r0 :irq_mod context0 Y% T( n* t0 ~
  146.     ; r1 :addr of from_thread's sp
    ( p" o5 c2 \& Z. R
  147.     ; r2 :addr of to_thread's sp
    " E  m6 f& Q4 A, k  W
  148.     ; r3 :to_thread's tcb
    $ j$ Z, L5 y# V( I

  149. : e, @) B) S0 k9 w* s
  150. 3 ~' @8 C: t( ]9 D- w/ y
  151.     ; r0 point to {r0-r3} in stack
    0 P0 ]. P. O5 C8 U
  152.     push    {r1 - r3}
    : p* e0 X. N% Z/ Q( {
  153.     mov     r1, r03 S% u. w$ I/ U( ?
  154.     add     r0, r0, #4*4/ S* I, B6 l" R3 J
  155.     ldmfd   r0!, {r4-r12,lr}; reload saved registers
      w8 o, D: j, T
  156.     mrs     r3,  spsr       ; get cpsr of interrupt thread  p0 x  V3 C  ]; i! Y
  157.     sub     r2,  lr, #4     ; save old task's pc to r2
    : a) H5 C  R/ E! T
  158.     msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
    ; H4 N; p9 b+ c0 @
  159. 8 A6 [! |4 O$ a2 _. i, w& L* f
  160.     stmfd   sp!, {r2}       ; push old task's pc
    ; C9 S* O7 Z$ `) [+ k! M4 L9 c& i
  161.     stmfd   sp!, {r4-r12,lr}; push old task's lr,r12-r4. _- w) w# }) ^* F# A  f
  162.     ldmfd   r1,  {r4-r7}    ; restore r0-r3 of the interrupt thread
    1 U' {% h+ w" q3 W5 |
  163.     stmfd   sp!, {r4-r7}    ; push old task's r0-r3
    . m1 \$ v+ o1 l" o! b' j7 }
  164.     stmfd   sp!, {r3}       ; push old task's cpsr+ a9 f& {8 u# F$ \
  165. & v: k% h  _* i; P6 `( m
  166. #ifdef RT_USING_LWP
    $ ^* {0 D% x) M* M+ r! [+ c6 y9 T
  167.     stmfd sp, {r13,r14}^    ;push usr_sp usr_lr: y: k9 ]& d, K4 r
  168.     sub sp, #8$ |! j* ~( ^4 q) c" r( U- F9 n
  169. #endif
    7 v. O4 [: v0 z& o: C9 L+ c9 V
  170. 0 ]; Y% w! M0 ~. U# f" e
  171.     msr     cpsr_c, #I_Bit|F_Bit|Mode_IRQ
    1 D  Z% V3 f! P+ L6 q' c5 M& J! x- ?
  172.     pop     {r1 - r3}) P* c2 `$ N4 d& l. P8 F, q
  173.     mov     sp, r0  j2 d: a4 h6 a, R, o
  174.     msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
    , X7 s* o, i' T! G" K
  175.     str     sp, [r1]. o# G' d% t$ T4 n7 x0 T2 R" t9 |( F6 Q
  176. $ r6 N# Z! ^; m/ w
  177.     ldr     sp, [r2]
    " E" k2 ]8 ^) X0 t5 M; \% G
  178.     mov     r0, r3+ P7 K5 u% w# }4 m
  179.     bl      rt_cpus_lock_status_restore  Y* \% z7 K! f/ m
  180. 4 W" k' l+ W8 j" u
  181. #ifdef RT_USING_LWP) J8 o# ?! i( Z, f3 Q7 ~0 }2 y
  182.     ldmfd sp, {r13,r14}^  ;pop usr_sp usr_lr
    0 M1 A- p3 ?" ^" @( q" w
  183.     add sp, #8
    3 x0 f7 v* `1 U' }
  184. #endif
    0 p- w) P2 m9 |0 a' }- l- f" _

  185. 4 S1 ^. W: v, e% _# P' [0 c
  186.     ldmfd   sp!, {r4}       ; pop new task's cpsr to spsr
    * d9 K0 ]" O: H* f
  187.     msr     spsr_cxsf, r4! t( m. L3 p5 l6 g" Z
  188. 5 J3 ~1 G0 g) G
  189.     ldmfd   sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr
    - F4 v8 t; R9 @$ e/ }' ~
  190. * {: \/ ?, B, w2 A! u9 _
  191. #else
    ) `# |$ {" e( k# u% B, B
  192. ;/*RT_USING_SMP*/# D. C  G4 g* K5 e
  193.     ldr r2, =rt_thread_switch_interrupt_flag
    / T2 o9 ~" k" X
  194.     ldr r3, [r2]
    9 x+ q2 v' d+ G0 k$ ?
  195.     cmp r3, #1
    0 }7 l  q: k, g5 {* _
  196.     beq _reswitch8 O1 J' E2 F* _8 O; k0 J0 g
  197.     ldr sp, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread9 |* m- D% B9 z# u! @4 m/ `
  198.     mov r3, #1              ; set rt_thread_switch_interrupt_flag to 1
    4 O$ W4 }2 e; ~6 e' Z
  199.     str r0, [sp]2 X. R( h* L$ K( [. t
  200.     str r3, [r2]
    5 x7 @$ Y6 f+ q3 x; J
  201. _reswitch:! {$ ~( w- ]% w& l  |9 g' t; V
  202.     ldr r2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread. ~. e3 Y$ q- {2 G$ Y
  203.     str r1, [r2]
    - n1 l: T2 f% I7 f# i
  204.     bx  lr
    4 R0 m7 C4 c. g& m" r7 R  w# p
  205. #endif
    ' [$ C/ }, K0 p) e$ o
  206. ;/*RT_USING_SMP*/& W8 [2 }7 q" ~9 @0 Z; g( `! T
  207. * `* k& U1 B4 ~
  208.         END
    4 {+ v$ e( M8 ~' A% X5 S. L
复制代码
QEMU_VEXPRESS_A9中的context.s是这样的
. p0 n! A" {1 k3 t
  1. #include "rtconfig.h", K2 K4 g: d  e  F7 O: q; w
  2. .section .text, "ax"
    $ V$ Z# |; h% O  M8 }6 E' T& q8 O

  3. ' j  n0 ?2 X% E( ~9 ?! K
  4. #ifdef RT_USING_SMP
    ' f, d% r7 P9 i8 Z: g+ B* N2 ?/ D
  5. #define rt_hw_interrupt_disable rt_hw_local_irq_disable
    $ h; e  [  R$ }3 J# ]7 d
  6. #define rt_hw_interrupt_enable  rt_hw_local_irq_enable
    5 ^& A2 m! \. J, z9 b0 i
  7. #endif
    ) B6 ?" ]! o7 x0 D5 \! b
  8. , S4 j( T5 e1 V4 n0 O2 b5 F
  9. /*
    $ a# J3 N  V( ^/ s, L
  10. * rt_base_t rt_hw_interrupt_disable();2 V# M; J4 g1 A7 \' y% \+ f
  11. */# c7 J' z7 {: w) @
  12. .globl rt_hw_interrupt_disable, Y; x0 a% \/ F# g1 ]  C2 u  o
  13. rt_hw_interrupt_disable:, K5 F9 U. ]; z  g4 N
  14.     mrs r0, cpsr2 D( O) d& q, l  V
  15.     cpsid i
    - _$ T+ z7 Q6 w, ]
  16.     bx  lr; c" u; Q3 G% \3 p* K

  17. 1 B) ]0 K' [( H' w
  18. /*; G( z, Q+ h1 y, _, R  A: x8 s
  19. * void rt_hw_interrupt_enable(rt_base_t level);
    % x7 h3 b7 }0 D0 |9 u
  20. */, j$ L: U4 U; K$ E6 x  u  [4 m
  21. .globl rt_hw_interrupt_enable3 q" F) g+ i" e
  22. rt_hw_interrupt_enable:
    3 R  C3 W7 \: t, {6 S) m
  23.     msr cpsr, r03 u7 B* j4 N) c( i, z- h: R# h/ s
  24.     bx  lr
    6 M- L; U& N( H9 X1 g( p

  25. ' d" \9 `! J5 i. l( b; Q
  26. /*1 t" ^1 P& w5 J( x. V2 r0 @
  27. * void rt_hw_context_switch_to(rt_uint32 to);
    * S- l. T% S& ~& T! ~& |# l
  28. * r0 --> to
    - Y: d( [3 n) |5 l
  29. */
    2 X$ ~% t# p' C  y3 U8 A
  30. .globl rt_hw_context_switch_to) ~1 v8 O3 w7 c3 v2 J
  31. rt_hw_context_switch_to:3 W4 R0 z( P1 K; J
  32.     ldr sp, [r0]            @ get new task stack pointer
    ! X$ o2 C3 E; k
  33. ! }: n2 }1 k$ u
  34. #ifdef RT_USING_SMP) v4 N+ K$ K, c# r4 |4 k$ s: X
  35.     mov     r0, r19 f# Y7 F8 }3 M" y- g2 s: q0 ]
  36.     bl      rt_cpus_lock_status_restore
    1 ^; l3 p# t8 S
  37. #endif /*RT_USING_SMP*/- Z% t& r7 j, W
  38. - J: m. j' [" [# R7 X
  39. #ifdef RT_USING_LWP
    2 q7 W/ W3 \  f7 m
  40.     ldmfd sp, {r13, r14}^   @ pop usr_sp usr_lr2 ]* `' e) k( C: Q, W2 Z# J
  41.     add sp, #8
    8 f7 u7 I8 Q' C' R+ E; s! j
  42. #endif/ [5 c3 G! R5 q" Q- G* k' d- n; \2 v

  43. 5 O1 k. ]/ S  c2 {( _; N6 I
  44.     ldmfd sp!, {r4}         @ pop new task spsr
    : j6 p/ d0 R! H4 O3 A# d
  45.     msr spsr_cxsf, r48 V' J- y0 _1 _% V" p+ q
  46. 1 P" y1 ^; w0 x, o" V) E! c
  47.     ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc+ Q* x9 h' E$ _, i9 g# s/ e
  48. 3 ?( k- _+ ?4 d( n" q8 w- g" W
  49. .section .bss.share.isr
    0 @& @9 F& f$ C* q6 o1 Y
  50. _guest_switch_lvl:
    4 a& d1 E( |4 T; {# ^. L
  51.     .word 0
    ! H- }6 H" v: w; y( |7 |

  52. * V7 X1 y- Y: t- a/ H
  53. .section .text.isr, "ax"0 h3 G  F7 e/ ]- J
  54. /*$ t* ]* j, k) X1 v  U3 |9 H
  55. * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
    ( V* [: {9 S! g7 M6 e: v  M
  56. * r0 --> from- q- [8 P2 W& U  ~" F
  57. * r1 --> to0 A2 s) ]" O' x( w* t
  58. */
    / o4 f6 Q" r/ K
  59. .globl rt_hw_context_switch& u* o) a" l/ {+ A( x6 Z
  60. rt_hw_context_switch:& S! z/ a+ t6 J8 R+ J" r
  61.     stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)1 V$ T6 L) }; U; A$ P
  62.     stmfd   sp!, {r0-r12, lr}   @ push lr & register file% V' |/ z3 Y) D3 P* Z

  63. , n2 u- ]: I$ U  ~  i& t
  64.     mrs r4, cpsr
    / x3 |  j( v1 `( h! [" G
  65.     tst lr, #0x01
    9 O) Y# T5 {. I0 i
  66.     orrne r4, r4, #0x20     @ it's thumb code) M0 T4 M+ B2 C* w; ^
  67. 2 ]/ [/ ?; w- ?! H7 r+ J
  68.     stmfd sp!, {r4}         @ push cpsr
    1 E* o/ @! A9 H5 h
  69. - i  d. ~6 A( c( S
  70. #ifdef RT_USING_LWP: R( y: m" H! M! a7 ^) T0 O- x' {
  71.     stmfd sp, {r13, r14}^   @ push usr_sp usr_lr
    8 J  k. c4 R; U$ _9 V9 m5 f/ k# c
  72.     sub sp, #8
    + n4 f2 g1 w& C% ~6 n# v/ O
  73. #endif% D7 @/ r1 j+ d" D! p% I

  74. 4 [: _; Z( |; {0 S/ d' b  }, _! v
  75.     str sp, [r0]            @ store sp in preempted tasks TCB3 f& l% I. V9 ]3 N( P) ?* P9 b
  76.     ldr sp, [r1]            @ get new task stack pointer
    5 N+ K9 ^( p0 n+ {
  77. # Y1 ?$ O- c* O
  78. #ifdef RT_USING_SMP
    6 E/ a% G: ~" Z0 m2 H6 f, B8 K
  79.     mov     r0, r2
    / @' \. Y* b, N0 A$ M
  80.     bl      rt_cpus_lock_status_restore% j) t$ {* L% w& N, K  X5 k
  81. #endif /*RT_USING_SMP*/; L& x. I* Q) M5 t# m7 \( g
  82. ) m3 R0 r8 M3 Y& z# E/ |. o0 x
  83. #ifdef RT_USING_LWP6 Q, X. ?2 D1 S( E
  84.     ldmfd sp, {r13, r14}^   @ pop usr_sp usr_lr2 F/ I7 O: L% n% {  a2 x
  85.     add sp, #8/ s+ F; T1 {9 F9 [* {# R
  86. #endif- [& g- B! E/ c% d

  87. 2 [8 r6 z% S5 U$ M9 G5 i0 G
  88.     ldmfd sp!, {r4}         @ pop new task cpsr to spsr$ c- A8 Q) [  R( t
  89.     msr spsr_cxsf, r4
    5 J  o. x0 L" f6 t5 ~0 g
  90.     ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr# i& d0 d2 T- I% R

  91. 5 d5 L1 T) n( y( b
  92. /*
    0 A) v2 l) L, f* {+ s
  93. * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);) e. s' [3 b: u' t3 C! {% ]# H
  94. */
    2 e& x& e9 Y. ]+ \
  95. .equ Mode_USR,        0x10# v9 V& g7 |7 `6 A
  96. .equ Mode_FIQ,        0x11( Z! ]; h3 c7 s" l* [' [
  97. .equ Mode_IRQ,        0x12
    & C  H, X$ l# ?
  98. .equ Mode_SVC,        0x13
    " W$ u5 f3 f6 Y  b6 o
  99. .equ Mode_ABT,        0x171 p% y3 S$ `4 m, V; ^, R
  100. .equ Mode_UND,        0x1B2 H  C7 s2 }6 \9 |, m/ m
  101. .equ Mode_SYS,        0x1F; \7 g& E. B" l
  102. 9 x1 W- ]' }* {2 q8 y+ T
  103. .equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
    9 Q; I# w$ Y( S4 M7 Z0 n
  104. .equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled# i3 v- _8 k5 J

  105. $ m! R# A1 R0 S0 _/ X2 L- A9 z
  106. .globl rt_thread_switch_interrupt_flag
    9 @- S4 [1 r6 {& a& r. X1 h3 [
  107. .globl rt_interrupt_from_thread
    ' \! H# d" o* Y7 Y4 J
  108. .globl rt_interrupt_to_thread
    - O4 C9 A2 p; ?3 j! n- \/ K
  109. .globl rt_hw_context_switch_interrupt
    ( N& T# M) o# m3 p" L
  110. rt_hw_context_switch_interrupt:
    3 S1 O: c0 A$ @) A
  111. #ifdef RT_USING_SMP1 e! m" p# r/ u1 H# B
  112.     /* r0 :irq_mod context1 d2 ?" k$ g  X( R
  113.      * r1 :addr of from_thread's sp% |8 a" ^" z5 ]
  114.      * r2 :addr of to_thread's sp( G: _4 R6 K- d" g0 `# _
  115.      * r3 :to_thread's tcb
    * r: z" l. B$ m
  116.      */2 R1 ]& x2 ]! v1 o4 f) n$ K% J

  117. 5 J1 y0 F  d1 K# l
  118.     @ r0 point to {r0-r3} in stack
    - j( N! n0 |  j7 ]5 g
  119.     push    {r1 - r3}
    7 ^8 n5 A2 f9 `% |
  120.     mov     r1, r0
    + u# t( M5 S5 s1 ?' v
  121.     add     r0, r0, #4*4, i& |% I8 {$ {
  122.     ldmfd   r0!, {r4-r12,lr}@ reload saved registers
      R: J$ |8 F& W4 A) ^- f
  123.     mrs     r3,  spsr       @ get cpsr of interrupt thread
    9 z+ c/ g1 S+ I( q! e' p
  124.     sub     r2,  lr, #4     @ save old task's pc to r2
    - G! Y- d8 U9 ^) S" O0 K! W
  125.     msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
    + S, z, M) }" D: H$ I; P
  126. , [$ h4 l5 e% \6 Q
  127.     stmfd   sp!, {r2}       @ push old task's pc
    , D$ p* ~) ^: T% h
  128.     stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
    6 \+ A, C" s3 O! `( i4 n- j
  129.     ldmfd   r1,  {r4-r7}    @ restore r0-r3 of the interrupt thread
    : R& ~! R1 ~/ F3 g' l+ F8 @1 t  W
  130.     stmfd   sp!, {r4-r7}    @ push old task's r0-r3
    : L2 g4 O( O' y# p7 J
  131.     stmfd   sp!, {r3}       @ push old task's cpsr
    % C9 l9 @# V! t3 l* B5 S
  132. & R, J. r  w5 `0 h
  133. #ifdef RT_USING_LWP2 ^! y, t3 t; W7 p2 b
  134.     stmfd sp, {r13,r14}^    @push usr_sp usr_lr& |3 D/ f$ T% |
  135.     sub sp, #8
    & |- O' }4 z& Y( f4 q
  136. #endif
    . f% a5 U) r; ]1 W6 O
  137. % U5 q" ~; A% y
  138.     msr     cpsr_c, #I_Bit|F_Bit|Mode_IRQ
    6 s- r* p9 u6 u( t- @
  139.     pop     {r1 - r3}9 A. @" L) _* [" U/ h! K
  140.     mov     sp, r0
    6 j* u3 b1 n0 O; h  S+ a
  141.     msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
    - M4 K2 v( \) v$ l) w0 n& V
  142.     str     sp, [r1]
    ) |. I, E8 S3 G% U

  143. & g" B2 r( i$ R0 p
  144.     ldr     sp, [r2]
    " t* W, X% |4 {: R3 D' a5 |: b
  145.     mov     r0, r34 H% ?  l6 t; S0 D$ F) D% a1 u
  146.     bl      rt_cpus_lock_status_restore
    6 ]; d2 }, \% d  L8 t# ?1 S6 ~
  147. ) H  X( i+ h$ Q, j
  148. #ifdef RT_USING_LWP
    , x8 b$ K" J# V! m3 `6 B/ O; Q
  149.     ldmfd sp, {r13,r14}^  @pop usr_sp usr_lr& S5 Q9 N# @9 F  L- c
  150.     add sp, #8
    ) ]' l* ^1 g/ M. |3 V9 A
  151. #endif) j& e& ?1 e5 e1 l. C, |  K

  152. * A6 e5 U+ o9 N# N. {7 M  I
  153.     ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
    : K* L) ~* H" j4 h
  154.     msr     spsr_cxsf, r4/ p: C% h8 J; w6 [5 ?
  155. 3 Y1 ^, v8 n" _- G* K" R
  156.     ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr  t; J9 a9 o& p: I
  157. 1 j7 ~8 V" i2 ^8 x9 P
  158. #else /*RT_USING_SMP*/4 Q8 k) ?3 J3 E1 r( P5 S5 A; u
  159.     ldr r2, =rt_thread_switch_interrupt_flag# p& K) g# f9 g/ x
  160.     ldr r3, [r2]
    8 B* C/ z% _  F5 W" v3 P
  161.     cmp r3, #17 Q; I8 W( {" P, O
  162.     beq _reswitch5 X7 l. j6 `( D2 l- F
  163.     ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread$ k5 [9 a) \7 ?% L4 c( B0 ~! e
  164.     mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
    : v2 q+ B5 ?& X* {! s! m
  165.     str r0, [ip]
    0 r' S0 U: h$ d7 B5 I! W% x) d3 [+ I
  166.     str r3, [r2]# W) a1 g* Z, l4 [' R4 ~
  167. _reswitch:* u- J7 f+ ?2 Q% U0 R. j  e4 o
  168.     ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
    2 ?0 z0 m: G* W
  169.     str r1, [r2]8 I1 [! E& |2 |) g4 N+ t7 ?8 |
  170.     bx  lr
    + Q* {- d* R; A, c( U
  171. #endif /*RT_USING_SMP*/
复制代码
弄了好几天一直卡在这,求大神指点7 ?+ H7 y( ?% K0 A" J
% k" L; P: v; v, @  G, E( s

1 R& t6 f1 K1 `- ]$ U+ l7 X5 A
2 V! l: |' \7 c- q7 \. S7 w" ^: p+ \5 u
2 ]" F4 o' F' Q: {$ G

3 Z. G- Q. T( x' x8 q3 N& N9 X
. d$ i$ T0 D8 H0 b4 U5 t* j* d% P1 y1 m: @! g5 s
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发表于 2019-4-24 12:31:39 | 显示全部楼层
多核版本?移植部分都弄好了?
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发表于 2019-4-24 13:08:24 | 显示全部楼层
bernard 发表于 2019-4-24 12:31$ K2 ?3 A: T0 b1 a! _/ J
多核版本?移植部分都弄好了?

+ @- |2 w0 j: |& A4 K- \! s 移植肯定弄好了 ,否则IAR编译也不能通过,原来是在不带系统的时候,改好了底层驱动,后来一点道移植到rt_thread上的,现在卡在这略尴尬,原来是我向老板推荐的这个系统,要是做不出来就坑了, I9 l2 u# P: _+ u$ ?, \5 N: Q! D- X
   beq _reswitch- _/ k- ?8 x, X" y" n% J
    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
' G3 |1 H3 F4 @8 \  ]( m8 Z    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 13 w4 J  ?8 D, S! t
    str r0, [ip]
5 T8 O* ~% E- R- b% Z/ X2 o    str r3, [r2]
/ O1 @* @7 e$ m: T8 N" `上面这段汇编里边有个困惑的if  ,为什么会用到ip寄存器,是不是写错了  arm里边没有ip寄存器吧
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发表于 2019-4-24 13:10:44 | 显示全部楼层
bernard 发表于 2019-4-24 12:31
/ {. C& P- q% D( a; T1 ]0 ~多核版本?移植部分都弄好了?

7 y; H8 C$ j& G2 j/ [原来在不带系统的情况下,就是基于imx给出SDK,自己实现了SPI通信,还有一些定时模块,现在要充分释放这块单核1GHz的四核板性难,必须找个开源的支持SMP的多核系统
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发表于 2019-4-24 13:12:18 | 显示全部楼层
hwx628 发表于 2019-4-24 13:08
( }0 Q0 P) t, g6 @8 A移植肯定弄好了 ,否则IAR编译也不能通过,原来是在不带系统的时候,改好了底层驱动,后来一点道移植到r ...

, x5 w5 {. P( v" W  }9 Y' l我把ip改成了SP才编译通过的,但是两个含义完全不一样,这个文件中在SMP模式下,就用的sp,为什么单核就突然冒出了ip
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发表于 2019-4-24 15:18:12 | 显示全部楼层
那你先用gcc跑通,跑起来吧
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发表于 2019-4-24 15:58:57 | 显示全部楼层
hwx628 发表于 2019-4-24 13:08
8 r7 A. p  z( o6 P# E移植肯定弄好了 ,否则IAR编译也不能通过,原来是在不带系统的时候,改好了底层驱动,后来一点道移植到r ...
& X; @3 E+ }0 n4 z* {, j5 k
移植做好不等于编译做好,这个是两个概念。需要底层的代码,汇编代码都处理好。多核部分,还和多核的启动方式也相关
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