在imx6q中到最后调用rt_system_scheduler_start总会出现undefined abort

发表在 Kernel2019-4-24 12:01 [复制链接] 6 159

  1. void rt_system_scheduler_start(void)4 z' c. W. g6 r! X5 [
  2. {- {  F+ M! L( O- T
  3.     register struct rt_thread *to_thread;1 b9 D9 `% O, q2 c4 o2 Z
  4.     rt_ubase_t highest_ready_priority;/ Z  ]) K% V/ S) g
  5. , ]- _$ M0 M$ Q* L/ u( H' K
  6.     to_thread = _get_highest_priority_thread(&highest_ready_priority);8 W  n" G  z& P9 q8 l) k, W0 \
  7. , ]1 U9 k1 W  X/ j- k6 k- f
  8. #ifdef RT_USING_SMP
    - L& z1 {7 |9 j; D* |7 n
  9.     to_thread->oncpu = rt_hw_cpu_id();$ o2 ^6 X: l2 }5 l3 J
  10. #else
    3 c) ~& v9 _$ D& g% J4 Q
  11.     rt_current_thread = to_thread;
    ; n4 r5 J( B; o9 D0 b( P
  12. #endif /*RT_USING_SMP*/$ m( Q# Z" h2 K8 r3 S8 B8 _

  13. + E$ D1 Q, R+ k( j- K
  14.     rt_schedule_remove_thread(to_thread);, N, n5 z, M% Z6 ~7 o% X1 M* G& Y$ m
  15.     to_thread->stat = RT_THREAD_RUNNING;! m: v4 M' a' w/ v# I+ [; `

  16. + ^- B- ~& |- e9 D$ y; H  v0 @
  17.     /* switch to new thread */
    * j* c' B8 b7 i
  18. #ifdef RT_USING_SMP
    7 t/ f4 [  n0 G
  19.     rt_hw_context_switch_to((rt_ubase_t)&to_thread->sp, to_thread);
    6 T8 V( Q1 V/ L" c& D
  20. #else
    1 B/ i3 A- M6 b
  21.     rt_hw_context_switch_to((rt_ubase_t)&to_thread->sp);
    3 Z, R3 ]- x5 r9 J) d4 Y% q* Q1 V
  22. #endif /*RT_USING_SMP*/5 c9 V" ^7 ?8 w% S

  23. / T( F/ O# z# P
  24.     /* never come back */6 w0 ?. X' k3 T( n4 G! }$ x7 N
  25. }
复制代码
#ifdef RT_USING_SMP. ?- A+ L9 G7 f* Q3 t7 S
    rt_hw_context_switch_to((rt_ubase_t)&to_thread->sp, to_thread);2 d1 b/ \* C# u
#else
& {; P; C4 W) B8 p) g3 Z) N3 |0 H    rt_hw_context_switch_to((rt_ubase_t)&to_thread->sp);
* Y5 D6 j2 e1 D: ~9 d3 ]- I5 U
$ r- u) e9 P0 c% b/ y用IAR DEBUG时,打断点发现每次一到这最后一句然后跳转到初始化过的  thread时,总会出现异常指令退出,rt_hw_context_switch_to 定义位于context.s参考的是qemu_vexpress_a9中的例子context_gcc.S,都是多核按理说这个应该是一致的,无须修改。
+ i# h- ]' c' U3 r, d下面给出修改过的适用于IAR的汇编文件context.s! {: E0 y) S- {# W* p
  1.         PUBLIC rt_hw_context_switch_interrupt
    % ]3 A/ V' t& Y0 _
  2.         PUBLIC rt_hw_context_switch
    " S$ _* T' `* O
  3.         PUBLIC rt_hw_context_switch_to! i- b3 }4 R, e" `1 l
  4. ;        PUBLIC rt_hw_interrupt_enable
    8 e) D" t) V* J- J, r3 t9 j( G
  5. ;        PUBLIC rt_hw_interrupt_disable" U8 G# {; ^+ t8 u1 j+ f8 ^

  6. 7 I! W: n/ \7 R
  7. 1 F5 E, W0 ?( A' J" R" ?8 f4 _" e: A1 P
  8.     SECTION .text:CODE:ROOT(2); H; z# C4 E' ?1 C) R! a
  9.         ARM
    6 ~- X' j& |. l8 l
  10.         IMPORT  rt_cpus_lock_status_restore
    " a, i' ]! T3 y0 o' k
  11.         IMPORT rt_interrupt_to_thread$ h8 ^; i: v) q; P0 ?/ d: ]
  12.         IMPORT rt_thread_switch_interrupt_flag% E4 E. o2 r; K6 ^7 p
  13.         IMPORT rt_interrupt_from_thread
    * m: y  E" u. k' I
  14. #include "rtconfig.h"
    7 N: y' W& ^) j/ G0 P2 `7 D4 e

  15. 2 i4 ?: }) Y1 {5 e& I. }
  16. #ifdef RT_USING_SMP
    - |- s1 v/ V! D* ~+ I8 w7 y
  17.         PUBLIC rt_hw_local_irq_enable( q5 c1 k) N- v) j6 @5 @& F4 ?
  18.         PUBLIC rt_hw_local_irq_disable
    1 b6 \/ v3 C. {7 u; z: w
  19. ; rt_base_t rt_hw_interrupt_disable();
    3 U: m7 p& D8 v* D2 S5 B; O

  20. 1 ?1 ]. e/ [  c& M9 A# A( s
  21. rt_hw_local_irq_disable:% {/ _7 M# j- z2 i' s) B
  22.     mrs r0, cpsr
    ) i& I$ |9 [5 T: A! t: W
  23.     cpsid i  T/ b" s) e$ o* X) ~0 S
  24.     bx  lr
    1 d8 W/ r0 W1 E! u% L/ ?
  25. 1 k" C7 }& J% s! s
  26. ;void rt_hw_interrupt_enable(rt_base_t level);
    / }2 W- z4 D# D' Z: Z7 V
  27.   Q# e0 H3 A. L( {& f
  28. 4 Y5 u7 y; @; i  ?
  29. rt_hw_local_irq_enable:+ U; @; `0 Z2 r
  30.     msr cpsr, r0
    - z( q1 U# _/ E( E" O0 W% g
  31.     bx  lr
    , Y* {/ ]0 B, Y9 J9 v7 p' g. E5 {3 G

  32. 6 ]  n8 G0 a; b" ?1 g8 f( o
  33. #else7 ^5 s  z( L/ ]! L. ?
  34.         PUBLIC rt_hw_interrupt_disable
    2 v# ?. \( m2 R! h# s
  35.         PUBLIC rt_hw_interrupt_enable( o* f* w. K6 U4 o0 O# @8 X& X' j
  36. + |1 g: \; k/ p" `. w
  37. ; rt_base_t rt_hw_interrupt_disable();+ a7 ^2 `0 X. e/ s/ I8 B: a, m
  38. + F* J+ ^) T% I/ r
  39. rt_hw_interrupt_disable:
    , x' n2 b6 U9 v2 P
  40.     mrs r0, cpsr
    & X: I8 O" z/ k7 q; ]6 L
  41.     cpsid i
    . a: y, d7 V7 }9 ]7 x$ u. o
  42.     bx  lr
    + L* C, f5 X) n' u2 J# M( m

  43. . {. W+ D1 E5 @3 ]- p
  44. 4 c2 z5 i( _% U7 [" A8 Q8 X
  45. ; void rt_hw_interrupt_enable(rt_base_t level);" c& M7 j& b* I) H! P% w1 @

  46. ' {# T! h0 }; S  H

  47. . I% c' M: \+ _; R7 I
  48. rt_hw_interrupt_enable:3 y) F, X$ @# W% \
  49.     msr cpsr, r0. _( m& z8 T' y& h6 r# I. K1 |! q
  50.     bx  lr
    9 M8 Q) ?8 d$ m- X; x4 e
  51. 0 ?4 I6 k7 b9 {; i3 M
  52. 8 U1 w' D- B) q' X
  53. #endif
    . o3 z, f0 {9 V2 d
  54. . C( i( h0 ^; J8 S/ j$ N* C/ u
  55. 6 S3 _- i% [, }2 L
  56. ; void rt_hw_context_switch_to(rt_ubase_t to, struct rt_thread *to_thread);# h7 p: T0 e/ `3 `9 K
  57. ; r0 --> to
    ( J) f" \$ g- u; Y
  58. % f' R& K4 }; Q! T& L- w

  59. ( w- v6 Y6 B- Q2 |$ G
  60. rt_hw_context_switch_to:' b8 ^  N9 I. U& B$ F$ w6 i/ Y6 O
  61.     ldr sp, [r0]            ; get new task stack pointer
    1 }7 L3 |3 q7 ~: v) c
  62. / i) p7 N- d! U: Y2 r  L8 v
  63. #ifdef RT_USING_SMP
    ' ~+ ]! S% m" j# h
  64.     mov     r0, r1
    9 Y# L: h: [$ E0 ^7 \! ?
  65.     bl      rt_cpus_lock_status_restore0 |0 \8 ~7 x* ^# k9 u# f7 w4 I  f- g. J  O
  66. #endif
    ; B  A# b; q$ D& Y, Z$ O
  67. ;/*RT_USING_SMP*/  _. B' U& O3 Q; k

  68. * o* t2 r, |, X7 S
  69. #ifdef RT_USING_LWP) P5 O# o& Z$ b' D- H! N
  70.     ldmfd sp, {r13, r14}^   ; pop usr_sp usr_lr5 [8 M$ J6 Q) E( F' ^- X
  71.     add sp, #8/ C& d  @& X6 E3 `
  72. #endif, E1 E( V9 F$ I2 s6 v
  73. ; M. E* Y; |+ E+ y5 X1 z
  74.     ldmfd sp!, {r4}         ; pop new task spsr! K- O6 B, J1 ?& m1 k3 |
  75.     msr spsr_cxsf, r4$ b" z( s# x+ D! ?5 ~6 `
  76. * R4 g! X! K, r( c) v# Q6 {2 }0 t# `
  77.     ldmfd sp!, {r0-r12, lr, pc}^   ; pop new task r0-r12, lr & pc
    % l+ }' T5 x. ^/ H
  78. ( R7 a6 L8 ?7 K, K" `. i( P& n! c
  79. ;.section .bss.share.isr2 w8 _+ v* c5 P2 B9 I/ j; i
  80. ;_guest_switch_lvl:
    0 `4 T7 e2 N) E% b* o# q) P3 Y
  81. ;   DCD 0
    5 C9 _9 B" b7 x2 |
  82. 7 a) f) P) o- Y9 c; }& R3 q  n
  83. ;.section .text.isr, "ax"9 g  t5 o) r" I. l! r) f& y
  84. # c% _1 U& w/ Q+ Y6 B! X

  85. * h7 M1 W0 m& K" B0 r
  86. ; void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);* }( h+ j. A6 R% P
  87. ; r0 --> from
    0 r" n! y. \% v; h/ l( r' X
  88. ; r1 --> to3 P: B( l3 [( n! }
  89. . p2 l. {) c$ A+ J+ B3 ^

  90. " ~$ _% r( B. U' V3 |# }
  91. rt_hw_context_switch:
    + V5 [8 r' m2 Y2 N6 ~0 j
  92.     stmfd   sp!, {lr}       ; push pc (lr should be pushed in place of PC)
    ) Q/ }& |( \+ G6 ]
  93.     stmfd   sp!, {r0-r12, lr}   ; push lr & register file
    * `; M1 ?6 y% q! o6 a, c  _2 w" t! A
  94. ! h  B; {4 o9 N4 d* \
  95.     mrs r4, cpsr
    ! R+ H0 r+ B1 ]! U# x0 y
  96.     tst lr, #0x01
    6 B3 W3 \; z" g% w$ m5 Q
  97.     orrne r4, r4, #0x20     ; it's thumb code2 T6 |* M$ l4 e9 z
  98. ' l, K2 O- c; p, S$ `5 W4 k
  99.     stmfd sp!, {r4}         ; push cpsr
    . @$ A' i( a1 b6 }1 P
  100. 8 ?& g, T  W. B: ^2 r. }
  101. #ifdef RT_USING_LWP
    ' e% {; `$ E2 I! \! A
  102.     stmfd sp, {r13, r14}^   ; push usr_sp usr_lr& Q3 `. [* U/ l
  103.     sub sp, #8
    5 z; ~+ m2 a, Y, [5 ]0 z. c
  104. #endif+ z7 V% t$ a% U7 N! a

  105. 6 B- a9 k! y- x* w/ I
  106.     str sp, [r0]            ; store sp in preempted tasks TCB( r& i. \7 e4 ~7 a2 e3 f5 I- w
  107.     ldr sp, [r1]            ; get new task stack pointer
    ' |5 L4 c0 L% G2 [( O. r9 E
  108. ' O" T. N/ D0 a% z8 o
  109. #ifdef RT_USING_SMP
    + f1 B  C' ~1 E5 ~+ u5 z
  110.     mov     r0, r25 x  h/ \" F6 H) @- v, n# |
  111.     bl      rt_cpus_lock_status_restore& a5 ~: k9 b# J5 h4 f% V
  112. #endif
    & B1 u# a- d0 K8 ^5 Y' O
  113. ;/*RT_USING_SMP*/$ V) t2 M' m0 k* j$ P* M" f
  114. 8 r. S% P6 J& Y. A
  115. #ifdef RT_USING_LWP
    ) R+ g3 p) Y1 ^) z
  116.     ldmfd sp, {r13, r14}^   ; pop usr_sp usr_lr! U7 ^; n/ r6 m. v
  117.     add sp, #8$ G0 ^9 S7 {) a
  118. #endif
    ! z8 N- @3 F+ `9 D' C

  119. 4 j$ C) y& n& `& v* O! T
  120.     ldmfd sp!, {r4}         ; pop new task cpsr to spsr& R- R% G( L6 E
  121.     msr spsr_cxsf, r4  K' F& v1 I+ V  V
  122.     ldmfd sp!, {r0-r12, lr, pc}^  ; pop new task r0-r12, lr & pc, copy spsr to cpsr
    3 u8 U( A, J( `9 }" g' M: L8 ^
  123. / V2 ]6 n1 Y/ h1 {9 J
  124. ) i8 H: y4 x+ x! s+ G& Q. v
  125.         #define Mode_USR        0x103 w: O) S5 Y3 K3 F4 z! ?
  126.         #define Mode_FIQ        0x11
    4 H0 k+ Q; A; B2 Q. R' Y; m4 }7 s
  127.         #define Mode_IRQ        0x12
    % P$ v' @* [8 B8 Y( N
  128.         #define Mode_SVC        0x13
    + K: {0 t! v  e% x$ E
  129.         #define Mode_ABT        0x17# _9 I9 t3 b( `: k3 K9 l: I. k% M
  130.         #define Mode_UND        0x1B
      a! Q4 y# X0 [4 V. q' K' L
  131.         #define Mode_SYS        0x1F% B8 X! E! q6 X

  132. 3 b  }* k  |3 Q' m  K8 y4 g
  133.         #define I_Bit           0x80
    : @! `4 d- d6 P5 ]# U- ^
  134.         ; when I bit is set, IRQ is disabled, t  h3 V% I; n
  135.         #define        F_Bit           0x40. l1 a  n1 P( J: O7 W+ p: F- u
  136.         ; when F bit is set, FIQ is disabled
      z; N) j' n6 Q# f

  137. 0 j9 k* Z9 B7 I  O
  138. , [8 ~5 {! F4 {5 O8 @* M/ L
  139. ; void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
      c( y1 C, [* T- e, Y4 F0 g
  140. & y; _! Q' p; O0 W# d) K5 Y7 S" @
  141. ; W1 L$ j& h( d5 X( t' W# o. N6 U
  142. - z+ o, t6 f9 Q1 q- m. n' L# D
  143. rt_hw_context_switch_interrupt:$ E* _2 Y" ~) W5 E7 k1 o
  144. #ifdef RT_USING_SMP
    ( p2 G+ Z, X* J& K# M) F( u
  145.     ; r0 :irq_mod context( v3 _" W6 a5 s7 u' O
  146.     ; r1 :addr of from_thread's sp
    . P6 s+ y5 S! S( U& l5 v" Y* L
  147.     ; r2 :addr of to_thread's sp
    ! x' B. G9 q9 h& t+ L, _" N
  148.     ; r3 :to_thread's tcb% N* \( Y8 S8 q7 V5 L

  149. 5 w7 C+ V& `" I3 s! p

  150. # ]& ]# M( c9 Y# F
  151.     ; r0 point to {r0-r3} in stack# n* \# h8 k; Z3 A# Z% \9 D
  152.     push    {r1 - r3}
    # X8 C& X8 O9 g0 S* I
  153.     mov     r1, r04 K3 f* [. P8 I4 s& e
  154.     add     r0, r0, #4*4
    : t' ~4 d& W, Y3 [% ^/ R7 @/ {
  155.     ldmfd   r0!, {r4-r12,lr}; reload saved registers. e/ E. v3 Z1 J0 }+ w  W# C
  156.     mrs     r3,  spsr       ; get cpsr of interrupt thread
    # c2 d9 _0 q& n- Y0 ^7 P) r" f! N
  157.     sub     r2,  lr, #4     ; save old task's pc to r2
    0 X2 F  {# Q! z! v
  158.     msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC+ Z$ @9 Y8 u* U2 m
  159. * U$ Z1 V2 Q7 A) S  a
  160.     stmfd   sp!, {r2}       ; push old task's pc& q& r+ }' X* x+ q$ r
  161.     stmfd   sp!, {r4-r12,lr}; push old task's lr,r12-r4
    9 g  v1 |: \: A( r
  162.     ldmfd   r1,  {r4-r7}    ; restore r0-r3 of the interrupt thread+ ^) Q6 D% u1 }7 Y7 ~
  163.     stmfd   sp!, {r4-r7}    ; push old task's r0-r3
    1 W/ l) {* s( k# E9 m0 z) B
  164.     stmfd   sp!, {r3}       ; push old task's cpsr
    . S3 X3 q. |: N+ H: S# N  N
  165. * ^$ g, w: }" k: \+ F1 w$ [& ~
  166. #ifdef RT_USING_LWP
    3 l1 W& F  J+ L! p5 w/ q
  167.     stmfd sp, {r13,r14}^    ;push usr_sp usr_lr3 n- c" ~5 j% p4 |
  168.     sub sp, #8
    " B$ p8 p. h( L
  169. #endif7 c1 r' D7 m7 {9 ]

  170. / r, T" ^4 `& S' q. E. V
  171.     msr     cpsr_c, #I_Bit|F_Bit|Mode_IRQ/ l) W+ x( b8 Q" M# W
  172.     pop     {r1 - r3}
    5 p( s- G: s) F" a% l' X
  173.     mov     sp, r0
    . d* f  q: Z3 M
  174.     msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
    $ e7 y3 p7 f: j1 l$ O* s' X: O
  175.     str     sp, [r1]6 N$ D  w- B# }& U
  176. 6 O, ]; H) |- p
  177.     ldr     sp, [r2]
      Z) ~9 e- ?7 D# c9 P" k. }
  178.     mov     r0, r3
    5 q( j6 v9 h9 B% C
  179.     bl      rt_cpus_lock_status_restore
    9 u7 @, L# z9 |$ R, Y4 w9 s

  180. , \4 }2 K. k% t, k  y7 f# L
  181. #ifdef RT_USING_LWP
    ; S9 }- }( V1 @+ `: G
  182.     ldmfd sp, {r13,r14}^  ;pop usr_sp usr_lr- _1 O- W; r, @5 x$ W" U2 H: V
  183.     add sp, #8
    6 X" q3 f) i$ K' }7 m5 y" n
  184. #endif' }. V* v6 T4 t

  185. / _! q8 }$ B0 G+ ?1 X
  186.     ldmfd   sp!, {r4}       ; pop new task's cpsr to spsr: ~" u9 B8 L6 |! W" I
  187.     msr     spsr_cxsf, r48 V- @6 {' q" C
  188. % Q4 T7 y$ U; C/ t$ @0 J2 n
  189.     ldmfd   sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr
    + ^  T6 u" L$ G& K! q, t/ Y

  190. : s/ t0 i3 |; S# u9 n0 ?
  191. #else4 o1 k1 g' \. s
  192. ;/*RT_USING_SMP*/
    : F5 }) S6 z# |1 k. ~
  193.     ldr r2, =rt_thread_switch_interrupt_flag: H- o& G0 ^1 ^# ~
  194.     ldr r3, [r2]0 J' D: \/ ~: H, ]  m: f0 B
  195.     cmp r3, #1
    9 I: m2 }0 K8 ?* y+ A
  196.     beq _reswitch0 A: }" i$ g# m# E+ O  Q) J
  197.     ldr sp, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
    . U+ B9 k4 D' ^) B# @1 A% z/ l% K
  198.     mov r3, #1              ; set rt_thread_switch_interrupt_flag to 1, T  a, u4 F! H+ e& o/ e
  199.     str r0, [sp]
    ) A7 ~% A  N$ A
  200.     str r3, [r2]1 V' |% \- _2 M4 A/ F0 q; h
  201. _reswitch:
    ( Y4 a$ W# Z6 P9 V) p
  202.     ldr r2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread
    * V3 s5 z- E( u2 p2 z
  203.     str r1, [r2]
    $ i0 L4 ^6 y0 t4 t* |& J. g
  204.     bx  lr- w( s2 k/ }; b& |% Z8 ]/ z
  205. #endif
    # O3 i0 m/ d0 L! K6 T" u- P7 R5 o
  206. ;/*RT_USING_SMP*/+ m) b# W+ j( S1 b

  207. " a# T- M) h- d# m; Q7 N
  208.         END! p+ x; q2 E" N) C
复制代码
QEMU_VEXPRESS_A9中的context.s是这样的8 S& K# \$ s  n% C0 S% H
  1. #include "rtconfig.h"
    6 f0 ?* S1 q" a& }2 r
  2. .section .text, "ax"
    : S: e- d# Z$ [* R+ m- S3 k7 b

  3. $ z; V& ^0 U9 Y% O  H
  4. #ifdef RT_USING_SMP
    ; ]6 X0 k4 T# c& |; m  c: Q
  5. #define rt_hw_interrupt_disable rt_hw_local_irq_disable! i8 U  ~( I  [6 n0 b) t
  6. #define rt_hw_interrupt_enable  rt_hw_local_irq_enable- o2 }- u% S: A1 M* X! l+ t+ b
  7. #endif/ o3 L! H, W# |) L3 X8 R
  8. 0 ]9 O8 K" @: p. U/ ^
  9. /*1 h  z' Q: B4 j; P6 G5 o
  10. * rt_base_t rt_hw_interrupt_disable();
    : Y, s* P7 A0 E" y! R6 P
  11. */1 w* i5 h  u4 V! W8 ~
  12. .globl rt_hw_interrupt_disable1 ^: M7 }- |' p) t: p1 t) b
  13. rt_hw_interrupt_disable:5 n4 Z, e8 r- `# H$ [
  14.     mrs r0, cpsr$ \' C; D+ I8 f- h4 P$ D$ p5 A
  15.     cpsid i
    % y9 Y& Z1 L2 [" x
  16.     bx  lr" S3 ]9 A  d7 y* M

  17. $ G* E+ X$ U! r
  18. /*0 M* `# Q, {! X4 _' B, n
  19. * void rt_hw_interrupt_enable(rt_base_t level);
    ' v1 Y' y& m( k% J: D3 P
  20. */, I% |( w% y- D: J
  21. .globl rt_hw_interrupt_enable
    % a( w9 P% D( V* X& z0 m& j, \6 }
  22. rt_hw_interrupt_enable:
      c5 A9 D+ c0 T8 N2 n3 `( i8 a
  23.     msr cpsr, r0" O( c1 y5 l  u6 g
  24.     bx  lr+ z' A" v' i6 m$ W

  25. 3 D6 x6 @- S  m/ U3 k7 i9 K
  26. /*
    $ Y+ R# P: A% k6 E' j* K6 u, I
  27. * void rt_hw_context_switch_to(rt_uint32 to);
    & p& g; ?8 V8 D5 U. D8 T+ v5 [2 ~
  28. * r0 --> to
    - u2 K- B  u, X2 c  Q! h
  29. */
    % B# r  f1 ~- r" h+ M! U4 Q& S
  30. .globl rt_hw_context_switch_to$ u9 r7 m! R3 z! Q# {0 F. s& r
  31. rt_hw_context_switch_to:
    - r  D4 @0 a1 A( p) {# B' q2 c
  32.     ldr sp, [r0]            @ get new task stack pointer9 Q6 V& w4 _2 X. S- F! c

  33.   ]/ p5 S( Y  L, r+ z  z0 _. q% |; J8 x
  34. #ifdef RT_USING_SMP/ j  Z! P# C4 T, g/ Y1 y9 f9 ]
  35.     mov     r0, r1, m4 ?  N% f+ J
  36.     bl      rt_cpus_lock_status_restore
    ( p4 f# _+ G+ a) }- r. \1 e
  37. #endif /*RT_USING_SMP*/
    # n! H" R4 r9 T! }( x
  38. $ n% J: o3 b9 v# l
  39. #ifdef RT_USING_LWP4 e. r7 O& V$ r5 J+ O
  40.     ldmfd sp, {r13, r14}^   @ pop usr_sp usr_lr
    + E4 D+ j% m/ x4 Y: j
  41.     add sp, #8( W( G5 O# ?& N& V/ `* ?) @
  42. #endif
    3 q# k' D, {3 d, H* C. h2 d2 |( I' i4 N. F

  43. 0 S& [/ G& r; z
  44.     ldmfd sp!, {r4}         @ pop new task spsr( |! G5 j4 P/ N/ ^. c
  45.     msr spsr_cxsf, r4
      v1 y4 ]5 o7 a

  46. / ]1 a7 s9 F% T7 U6 S4 {
  47.     ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc1 Y' |, c/ f$ I2 b4 V
  48. : R! ?. M' ]# D/ j  s: Y6 Z+ O
  49. .section .bss.share.isr, o& ]. k! N1 K' a; x- z9 H
  50. _guest_switch_lvl:2 F, C$ @6 j( Y5 d2 G* g1 G7 i
  51.     .word 0! e8 ~& f' w, C

  52. & k4 p" @  Y9 A, _/ U* J! l
  53. .section .text.isr, "ax"
    ! O/ Y$ D; u% u- [
  54. /** i7 q2 O4 y- U; \5 ^
  55. * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
    * x9 f2 O. @" }1 Y
  56. * r0 --> from
    ; C# m6 F* a  s0 z2 a5 {! n
  57. * r1 --> to. K8 {* v& x6 V6 r7 E; K4 N, x' L
  58. */
    8 u" ~- g+ B/ c$ y
  59. .globl rt_hw_context_switch
    - b% e3 ^9 c  w
  60. rt_hw_context_switch:
    7 J8 Y  z9 s7 m) o( y. L
  61.     stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)* \& R  f5 x0 O/ l* |2 K' S$ |/ }: S  r$ ~
  62.     stmfd   sp!, {r0-r12, lr}   @ push lr & register file
    : {9 m1 r& H  O" i& R. |- B, G7 j

  63. 5 }6 A1 [4 V5 `& Y; {! X1 I
  64.     mrs r4, cpsr3 B$ I' x, N7 R. p+ }
  65.     tst lr, #0x01
    . ]" M1 h4 F/ ^
  66.     orrne r4, r4, #0x20     @ it's thumb code2 F' J: ?9 l% {- `; g5 V

  67. ' ]; @6 d0 D8 z1 ^, w
  68.     stmfd sp!, {r4}         @ push cpsr
    8 g8 b: R9 k8 A: i
  69. 7 x5 P/ R6 L" ]3 a6 P
  70. #ifdef RT_USING_LWP
    4 ]1 N: d: Q# r3 N$ \2 n, e
  71.     stmfd sp, {r13, r14}^   @ push usr_sp usr_lr3 Z4 x0 a. c7 ~
  72.     sub sp, #8# h) q0 ]( I# j( }  p2 \
  73. #endif
    ! Q1 H( X& o% e0 u: q! u

  74. / H- g2 m3 |, ~% ~6 a% u
  75.     str sp, [r0]            @ store sp in preempted tasks TCB
    5 E9 J% W. _- P& i& y) R: J6 F
  76.     ldr sp, [r1]            @ get new task stack pointer
    ( `! N' u: o5 ]& }$ O

  77. / Z5 I9 D, t2 x! F/ j0 N
  78. #ifdef RT_USING_SMP4 G) Z) `% q4 C8 P+ S* E! O
  79.     mov     r0, r2
    / P  L3 o7 Y/ q3 D) B5 g  S( X+ K
  80.     bl      rt_cpus_lock_status_restore
    1 t1 @7 f6 N6 R# G3 _- r' c
  81. #endif /*RT_USING_SMP*/# y. A: ~" e& I8 {( U8 `  ~  o

  82. 1 l/ F+ }* N8 i9 P5 _6 O" O$ ^
  83. #ifdef RT_USING_LWP
    - I# n( L6 Y8 M& y5 B( A
  84.     ldmfd sp, {r13, r14}^   @ pop usr_sp usr_lr7 j! P; s! J2 S4 m
  85.     add sp, #8# z! E" A3 n8 r
  86. #endif
    + u+ z* ~+ Y, |
  87. 3 Z) @  U0 Z4 r8 I$ m, M1 h
  88.     ldmfd sp!, {r4}         @ pop new task cpsr to spsr
    6 G+ W0 \# S. d2 L  G% {) j
  89.     msr spsr_cxsf, r44 y: m' h3 L8 x% s( Z4 e
  90.     ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr& o: a( L) A: d  e" b+ ^
  91. . H. L) k( b1 a
  92. /*
    0 H3 T7 `9 j8 G; z& ~8 A- ]
  93. * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);5 }7 A7 q: U6 p% {9 w8 K
  94. */3 z, P, a" ]# H+ p  J
  95. .equ Mode_USR,        0x10
    5 X0 a! O  T  p9 x# W
  96. .equ Mode_FIQ,        0x11
    - `& |: o( f% O2 Z  B
  97. .equ Mode_IRQ,        0x12( c/ g  R3 b! {* S% `* O
  98. .equ Mode_SVC,        0x130 h* ]7 z) [, P+ ~# A
  99. .equ Mode_ABT,        0x17
    " {# C; @/ e8 }, h
  100. .equ Mode_UND,        0x1B: q( w' d; _  k5 X1 ?4 n
  101. .equ Mode_SYS,        0x1F
    & X2 S) b  X. q' |/ v6 ]* h

  102. 8 q" f4 x; C2 _8 d- }# u8 ?
  103. .equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
    8 n0 V  D' f2 x! P2 r/ s
  104. .equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled9 j7 u( L$ ~$ D- |1 d' u

  105. # i& j  E$ h. Y; A; J6 u7 c
  106. .globl rt_thread_switch_interrupt_flag
    + |# T% B& `8 r4 v9 R5 ~5 J1 ?8 Z1 J
  107. .globl rt_interrupt_from_thread
    ! J& o, @* ^. _2 F0 A/ y/ w  @' m
  108. .globl rt_interrupt_to_thread& n0 \* A, F' Z% ~. \# A
  109. .globl rt_hw_context_switch_interrupt
    ; X. `, c8 b) L, R4 e' b/ Y) Z2 a) O
  110. rt_hw_context_switch_interrupt:/ Y. d" s: w+ H! e8 ~
  111. #ifdef RT_USING_SMP. m: e' R( Z& \3 y
  112.     /* r0 :irq_mod context, Q0 k0 h! @8 Z# G* e7 y8 v  b# }
  113.      * r1 :addr of from_thread's sp8 }$ L: F" |) y" U) g4 r: u
  114.      * r2 :addr of to_thread's sp5 N; V7 H" q! O# t1 f; ^2 [# x" E
  115.      * r3 :to_thread's tcb7 O- `$ P' Y5 M0 T+ T7 N0 r0 Z
  116.      */
    , c! A- g2 N/ }: x& A
  117. 2 C! q3 E1 n* ^  Z7 _
  118.     @ r0 point to {r0-r3} in stack
    . Z: H! V: f; V- W" i- }
  119.     push    {r1 - r3}
    & _" j4 O' z* B. v4 g
  120.     mov     r1, r0
    1 P$ C& Y1 p/ ^2 L( T
  121.     add     r0, r0, #4*4
    ( F1 f4 l* M" v; J
  122.     ldmfd   r0!, {r4-r12,lr}@ reload saved registers. T" B0 D$ }# }9 t( B- y
  123.     mrs     r3,  spsr       @ get cpsr of interrupt thread5 ]1 A  M  O# X& A. H
  124.     sub     r2,  lr, #4     @ save old task's pc to r2
    ) R' r- ?9 f0 s3 U4 a
  125.     msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC) h. F" T! P. b
  126. ; b/ f' ]5 z- U% I7 _% j  Y
  127.     stmfd   sp!, {r2}       @ push old task's pc( F. Z+ b& g( v
  128.     stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
    6 j" c4 e# Y/ w8 K
  129.     ldmfd   r1,  {r4-r7}    @ restore r0-r3 of the interrupt thread0 X6 S+ G5 y# {. i. {
  130.     stmfd   sp!, {r4-r7}    @ push old task's r0-r3
    $ x9 j" [7 o% I, e
  131.     stmfd   sp!, {r3}       @ push old task's cpsr
    7 P5 r1 t7 O7 X' a$ M
  132. . L4 r1 R) L1 L$ h8 e) F, R
  133. #ifdef RT_USING_LWP7 Z8 ]* h: ]2 q' h" v
  134.     stmfd sp, {r13,r14}^    @push usr_sp usr_lr
    / F. k. F" m& I& N7 i
  135.     sub sp, #8& z2 t, z" h( |
  136. #endif# }4 [* q& |) V: j
  137. 1 M$ z) z' p$ j
  138.     msr     cpsr_c, #I_Bit|F_Bit|Mode_IRQ
    6 l8 q8 g& Y. j" J1 q9 f$ H7 G
  139.     pop     {r1 - r3}
    0 x) ~/ \! X& n' u! Z
  140.     mov     sp, r02 V; V3 k! `" S- ^8 ^
  141.     msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
    : d# b% c# ~, T  Y& p  U
  142.     str     sp, [r1]
      K6 M9 k, l2 e, u' x% d; h, }% p
  143. 7 F+ s. F. d% \
  144.     ldr     sp, [r2]
    7 c! p  C; v, R/ b( S3 d* G& Z# B
  145.     mov     r0, r3
    7 c0 K$ ?* }" }  N7 n. e/ d
  146.     bl      rt_cpus_lock_status_restore' t' Z2 K# n9 x" u* s% R

  147. 8 h: s0 q! Z; o6 w
  148. #ifdef RT_USING_LWP" ?! P/ N' Y- V! M* i
  149.     ldmfd sp, {r13,r14}^  @pop usr_sp usr_lr, n- R- D" s% r# P1 d" ]% ?
  150.     add sp, #8
    7 Q# d/ |" O: j! T" j8 d
  151. #endif' `  l; b4 e0 @; h" G
  152. * w: j; N7 i! F# g: H
  153.     ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
    2 [: i: h1 b$ Q$ k
  154.     msr     spsr_cxsf, r4
    3 {5 c# T" ?4 v1 q; W

  155. $ R& ^- `7 h( k' N. {; _
  156.     ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
    3 i. y0 s; l+ O; l6 \. ?
  157. - |+ S% B( x& ]6 J1 o
  158. #else /*RT_USING_SMP*/
    + v7 _# q* `' v1 z
  159.     ldr r2, =rt_thread_switch_interrupt_flag1 U" P3 I3 m  I. r" c, I. J2 |
  160.     ldr r3, [r2]
    % `# ?1 [9 l$ J0 g. x2 j/ ~
  161.     cmp r3, #1% }* w4 e4 K( m/ d# V! b" C
  162.     beq _reswitch  f- |5 }% L) ~5 t+ `* M6 z
  163.     ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread: c0 J+ n/ h/ b" Z
  164.     mov r3, #1              @ set rt_thread_switch_interrupt_flag to 10 J' t( ^" A% y* Y$ G8 u5 f7 x
  165.     str r0, [ip]
    - u7 v4 n, _6 c& n4 X$ k) M
  166.     str r3, [r2]
    % j) A% s8 w$ f$ y2 s/ K
  167. _reswitch:: M/ |0 V0 X* a7 T4 E# V
  168.     ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread0 O4 p1 p4 h6 x1 Q* K* a5 r& k
  169.     str r1, [r2]
    3 P3 n3 q/ k6 O4 z# k! n; p2 ^
  170.     bx  lr3 ]1 I9 q6 q9 }& C
  171. #endif /*RT_USING_SMP*/
复制代码
弄了好几天一直卡在这,求大神指点
5 {$ U3 R9 N" N+ v0 b* E1 ^6 K! R9 k

$ H, d! L" p6 I' L
% n$ i/ `: B. c: d  K9 G5 U% |- s* T6 j. \8 \5 q2 O  ~. A' R
8 K, I0 \6 `# E

! I7 o: ~; K4 v- ~4 f+ K3 {
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发表于 2019-4-24 12:31:39 | 显示全部楼层
多核版本?移植部分都弄好了?
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发表于 2019-4-24 13:08:24 | 显示全部楼层
bernard 发表于 2019-4-24 12:31+ D$ n0 t5 O- w6 ]4 q- {; D
多核版本?移植部分都弄好了?
7 w& D- B3 |3 L* P+ r$ K" r
移植肯定弄好了 ,否则IAR编译也不能通过,原来是在不带系统的时候,改好了底层驱动,后来一点道移植到rt_thread上的,现在卡在这略尴尬,原来是我向老板推荐的这个系统,要是做不出来就坑了
% F5 b: g' [9 Q3 ~* n! ~   beq _reswitch
& k2 {2 n# b* ^* s5 G. G* Y" \  b3 p    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
# N* ?; T3 U2 t" y    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1' y1 m! P& K: E% z6 v+ v
    str r0, [ip]
' M- U! w% N" l$ _' t; Z5 J    str r3, [r2]
5 ~4 D. S- I+ S上面这段汇编里边有个困惑的if  ,为什么会用到ip寄存器,是不是写错了  arm里边没有ip寄存器吧
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发表于 2019-4-24 13:10:44 | 显示全部楼层
bernard 发表于 2019-4-24 12:31
8 a; M  ]$ \, d! \多核版本?移植部分都弄好了?

( E5 r: D$ m3 c) `8 X原来在不带系统的情况下,就是基于imx给出SDK,自己实现了SPI通信,还有一些定时模块,现在要充分释放这块单核1GHz的四核板性难,必须找个开源的支持SMP的多核系统
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发表于 2019-4-24 13:12:18 | 显示全部楼层
hwx628 发表于 2019-4-24 13:08
* k* z+ j% Z3 r  j移植肯定弄好了 ,否则IAR编译也不能通过,原来是在不带系统的时候,改好了底层驱动,后来一点道移植到r ...
" D. L  D. M6 Q
我把ip改成了SP才编译通过的,但是两个含义完全不一样,这个文件中在SMP模式下,就用的sp,为什么单核就突然冒出了ip
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发表于 2019-4-24 15:18:12 | 显示全部楼层
那你先用gcc跑通,跑起来吧
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发表于 2019-4-24 15:58:57 | 显示全部楼层
hwx628 发表于 2019-4-24 13:08% D3 W0 n) d2 P) ]
移植肯定弄好了 ,否则IAR编译也不能通过,原来是在不带系统的时候,改好了底层驱动,后来一点道移植到r ...

4 l+ P% M5 i  T+ w移植做好不等于编译做好,这个是两个概念。需要底层的代码,汇编代码都处理好。多核部分,还和多核的启动方式也相关
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