在imx6q中到最后调用rt_system_scheduler_start总会出现undefined abort

发表在 Kernel2019-4-24 12:01 [复制链接] 6 81

  1. void rt_system_scheduler_start(void)( q9 c2 ?8 Z3 o9 o" e- _
  2. {
    ( |$ ^5 O+ O. y' L
  3.     register struct rt_thread *to_thread;
    # i* X1 B& z' S# X
  4.     rt_ubase_t highest_ready_priority;3 H3 U4 H8 l! x0 x) m
  5. 3 S3 V7 t: R2 B7 m6 ^" y7 U1 j4 x
  6.     to_thread = _get_highest_priority_thread(&highest_ready_priority);
    8 z) }6 v, }4 p) u# n) V5 m; r

  7. ) u0 }+ h( S$ E
  8. #ifdef RT_USING_SMP
    # ]& Z9 Q- O6 t5 x4 v% z' e
  9.     to_thread->oncpu = rt_hw_cpu_id();" g) S9 J; P; P+ G- a$ t6 {
  10. #else: @, L- q* r5 k+ Y/ p% [
  11.     rt_current_thread = to_thread;
    0 {9 n# j) \0 Y
  12. #endif /*RT_USING_SMP*/
    + T0 i9 p- K; h4 S+ Z) o4 r' w3 L

  13. / @- q& j0 J! a/ V* Q6 E& x0 E
  14.     rt_schedule_remove_thread(to_thread);0 ~( E  L" h9 K3 T- l
  15.     to_thread->stat = RT_THREAD_RUNNING;4 N3 m: E! q$ b% @7 [
  16. ) W+ @) l2 _1 L3 j+ [; [
  17.     /* switch to new thread */2 j* d2 I4 Q8 _1 r3 o- J2 B2 b
  18. #ifdef RT_USING_SMP
    / w9 T3 L( D4 K' ?+ z2 }
  19.     rt_hw_context_switch_to((rt_ubase_t)&to_thread->sp, to_thread);
    6 n) I# p: J, d5 d/ `
  20. #else/ i, \% C5 B' j
  21.     rt_hw_context_switch_to((rt_ubase_t)&to_thread->sp);
    0 i" W, f% s  T( o5 |! Q# t, E
  22. #endif /*RT_USING_SMP*/' z. L. n; l: E5 N7 b; h  y% c

  23. # i( g1 I6 q2 N# f8 }
  24.     /* never come back */
    6 N( j  o6 [; S1 e5 a0 u
  25. }
复制代码
#ifdef RT_USING_SMP& ~; j- b) z; m$ I& g
    rt_hw_context_switch_to((rt_ubase_t)&to_thread->sp, to_thread);: K9 w* F  Y1 S% J
#else
$ x) o9 L0 X6 Y2 i    rt_hw_context_switch_to((rt_ubase_t)&to_thread->sp);
0 Z, |2 Q0 q( V( t6 b) r0 K( k7 H8 c6 _0 B2 @* P! \( X
用IAR DEBUG时,打断点发现每次一到这最后一句然后跳转到初始化过的  thread时,总会出现异常指令退出,rt_hw_context_switch_to 定义位于context.s参考的是qemu_vexpress_a9中的例子context_gcc.S,都是多核按理说这个应该是一致的,无须修改。
2 ?& c- V3 Y- l( [* e, u/ K0 V下面给出修改过的适用于IAR的汇编文件context.s
# s+ Q4 Z) R3 m. [4 o
  1.         PUBLIC rt_hw_context_switch_interrupt0 ?3 r8 L4 L% l- k3 y
  2.         PUBLIC rt_hw_context_switch) X5 t# H5 f* s' _7 m* g0 g+ O
  3.         PUBLIC rt_hw_context_switch_to, u1 u3 W# `! h' |" Z9 ]. }5 f
  4. ;        PUBLIC rt_hw_interrupt_enable
    7 n7 F5 u  b/ ?
  5. ;        PUBLIC rt_hw_interrupt_disable
    4 U$ l$ I9 z% \- m1 R8 F1 @6 k' T
  6. . B" K* X% s  ~+ u2 S/ q

  7. ) L, E% T4 S6 `# M3 D, L8 l1 B: Y
  8.     SECTION .text:CODE:ROOT(2)) h" ~+ \+ E) y. c( X
  9.         ARM
    1 {+ P7 ?- \; k; [2 ~+ @/ A$ l3 E
  10.         IMPORT  rt_cpus_lock_status_restore
    $ y. q3 L( J4 o# o
  11.         IMPORT rt_interrupt_to_thread
    0 u7 u. P! z0 }1 z3 d
  12.         IMPORT rt_thread_switch_interrupt_flag8 `/ R8 E( W# d3 n  j9 h, h
  13.         IMPORT rt_interrupt_from_thread  Q+ b! J; S. P. j; b0 A
  14. #include "rtconfig.h"
    - Y7 ^; g, }6 s# ]+ r5 c$ l
  15. : ~4 b. N, P) V" v8 ?4 O# e$ b6 E7 J
  16. #ifdef RT_USING_SMP. y# z- i7 \/ p: I, N
  17.         PUBLIC rt_hw_local_irq_enable
    " s' k; V1 P- s; }+ V* @) Y
  18.         PUBLIC rt_hw_local_irq_disable4 r; g" g9 u' H. l- t: V  e6 }
  19. ; rt_base_t rt_hw_interrupt_disable();$ a. W7 S& t  M, L* _
  20. ; x, M) ~( s3 O4 P3 R$ x
  21. rt_hw_local_irq_disable:) V* e2 m# p. u  b, G
  22.     mrs r0, cpsr8 N4 ]  g( ~0 w: Q0 e0 W
  23.     cpsid i
    3 b  @. ^# A7 t. k8 Y
  24.     bx  lr
    # }* b: o" y( Y) m% c

  25.   ~- U5 N3 M$ s- |' n* d2 m
  26. ;void rt_hw_interrupt_enable(rt_base_t level);2 P6 E3 ~" F9 v
  27. . H! {3 w+ `$ D7 p. a- S( U2 d# s
  28. 1 V1 l- {  J2 r; G, C3 V2 D
  29. rt_hw_local_irq_enable:
      l" L; `1 z& }; Y- ]6 B$ C
  30.     msr cpsr, r06 p2 K" X5 k6 z) E
  31.     bx  lr; d6 |+ e3 C/ O# v6 ^
  32. ) _# n% [/ U- q7 w; q2 H$ n
  33. #else, E7 ~& g' R3 d
  34.         PUBLIC rt_hw_interrupt_disable
    1 C; c. C- i# U
  35.         PUBLIC rt_hw_interrupt_enable
    ( L9 s4 `* y0 k! Z, E& r

  36. . u- ~  o1 j2 l* J! A! u
  37. ; rt_base_t rt_hw_interrupt_disable();
    3 ~$ a  W4 [9 J0 M. Q
  38. * B5 e0 I+ @+ X% C
  39. rt_hw_interrupt_disable:! r( l: [6 A- R3 G8 q$ o5 O0 d. ^
  40.     mrs r0, cpsr4 t1 J9 H$ D# l; }
  41.     cpsid i
    ) z" X1 s7 F: ~
  42.     bx  lr, C) F+ f5 |* A- }5 @
  43. % L0 w$ w( E% v: o3 |
  44. 8 x4 m! `7 [' L7 T% A: F; P( F; l7 \
  45. ; void rt_hw_interrupt_enable(rt_base_t level);$ o; b0 w( |/ G" _5 q, ]

  46. 9 a8 V1 p2 M# j7 e  Q
  47. + {! [2 ]2 N0 B
  48. rt_hw_interrupt_enable:
    ' w1 R. _/ P1 k6 q# J
  49.     msr cpsr, r0, p  t, g: r4 x
  50.     bx  lr
    * s# S! q1 i- b7 M5 b
  51. ! L" R6 ~8 x: v- b

  52. 1 X, A3 D8 y. t  Y4 ?
  53. #endif
    & e5 Y1 |8 Z) K. ?( i
  54. , K% c5 @( _5 c2 ^. `7 C1 c# X0 F+ u

  55. 4 ]2 s5 u4 o0 @/ L1 u
  56. ; void rt_hw_context_switch_to(rt_ubase_t to, struct rt_thread *to_thread);
    3 s# [; o+ B" [( F
  57. ; r0 --> to0 o2 X9 x/ |% |. U2 b$ I

  58. 1 b4 n% X* O$ r* X5 ^, z
  59. & m& J! L  q, m6 `1 ~' s9 n
  60. rt_hw_context_switch_to:5 W( [! X! q& f' k
  61.     ldr sp, [r0]            ; get new task stack pointer& R* r9 Q$ ~/ i9 B7 m0 |  R

  62. 8 ~/ Z2 b! y# R% E$ _1 I
  63. #ifdef RT_USING_SMP5 t' O0 B$ z. a
  64.     mov     r0, r1
    : ^/ \! s2 G" F0 v% n- V
  65.     bl      rt_cpus_lock_status_restore
    . @6 C9 I2 Y, a/ Y3 }
  66. #endif2 r7 Y* ?1 Y  P7 C. \! {
  67. ;/*RT_USING_SMP*/
    ; v* u( T- \  Y% f! `% r
  68. 3 z1 E* ]% v& i5 L# n% \9 Z
  69. #ifdef RT_USING_LWP: _( I: y  J  {4 l7 d7 x+ \
  70.     ldmfd sp, {r13, r14}^   ; pop usr_sp usr_lr2 T- L% t( {! O5 m/ P
  71.     add sp, #8
    6 y+ t: I! Q1 D" v; y$ E  g+ J# U
  72. #endif4 D7 x1 W) K4 E$ ?

  73. 6 d/ P* k% }( w. n
  74.     ldmfd sp!, {r4}         ; pop new task spsr
    7 q6 ]; f; j9 e; r, k2 p% n7 c, Y
  75.     msr spsr_cxsf, r4) C; b2 K$ `1 B: U$ s, a
  76. 5 {9 V1 _9 l! j3 Q6 p4 k# n: w
  77.     ldmfd sp!, {r0-r12, lr, pc}^   ; pop new task r0-r12, lr & pc
    " K6 M  ]* l7 g5 Y9 ]' L

  78. ! p3 y8 a. `: S' P) ?) V& b9 h
  79. ;.section .bss.share.isr/ _7 z, w9 s/ x9 ]" u" M/ l, o
  80. ;_guest_switch_lvl:7 Y1 a) n) {# O8 {
  81. ;   DCD 0
    ! S! [4 i$ j* A$ m
  82. ! m5 q  R+ s7 V$ z7 \
  83. ;.section .text.isr, "ax"
    - s8 k7 w* t; p. b# N6 K- w6 I

  84. 3 F; }  Y& O) s/ I2 s7 Q
  85. % @5 }* N9 l3 }  a1 t0 h- m4 M
  86. ; void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);! s! h& R4 l6 T) ?" m6 [
  87. ; r0 --> from
    / f: l+ r3 N4 R# _0 p" |7 i
  88. ; r1 --> to
    9 T' }7 }" \+ ~

  89. 5 R) d/ Y' g6 N, C7 y8 p
  90. & p6 V. z' W6 C* r+ \
  91. rt_hw_context_switch:0 y& @! o6 u# U3 Q% w8 i
  92.     stmfd   sp!, {lr}       ; push pc (lr should be pushed in place of PC)+ M. h9 o6 [4 Q
  93.     stmfd   sp!, {r0-r12, lr}   ; push lr & register file: G- H# ]- C) u! ?" x" t' @0 E

  94. & ^3 f3 [9 Q. B0 }- f# x
  95.     mrs r4, cpsr
    ; ~9 R% N3 |# c
  96.     tst lr, #0x01
    3 f3 z# Q4 ]0 t, s, T  t  e
  97.     orrne r4, r4, #0x20     ; it's thumb code) Z$ o4 h; s. n8 N; d  m* h$ i
  98. ( Y! s! p0 {- X& M3 K. }& ]
  99.     stmfd sp!, {r4}         ; push cpsr. ^4 k8 G# Y- g  ~
  100. . D& p# p; v9 t1 I. u) H
  101. #ifdef RT_USING_LWP
    & r) W# t$ u$ v9 q+ d& q' u1 z
  102.     stmfd sp, {r13, r14}^   ; push usr_sp usr_lr& s( S7 x$ b. [
  103.     sub sp, #8  m. H- [9 P$ F3 l
  104. #endif
    1 H# a2 X% `; x. n! D% ^6 B

  105. , G  T1 M& O0 \/ l  r7 h  ]7 E
  106.     str sp, [r0]            ; store sp in preempted tasks TCB8 m! v3 p* V6 v; X
  107.     ldr sp, [r1]            ; get new task stack pointer! N8 l' {; [/ b3 T" T* ?+ l6 h

  108. : g0 y. m3 M  g+ r0 g& H
  109. #ifdef RT_USING_SMP
    3 |: `+ P2 k. ~% f& Q8 }
  110.     mov     r0, r2
    - t# ~. H2 D: z
  111.     bl      rt_cpus_lock_status_restore3 f& _( x: ?  [4 l
  112. #endif
    / u7 I# `: b- [2 R
  113. ;/*RT_USING_SMP*/
    8 ~: i$ n$ M8 g) F  h

  114. $ a' V* A/ L: X
  115. #ifdef RT_USING_LWP
    ( y' ~- y5 y  w( }( m
  116.     ldmfd sp, {r13, r14}^   ; pop usr_sp usr_lr
    4 S: B$ d5 ~& y9 J2 J0 E9 e& V
  117.     add sp, #8
    , i+ u. m- p7 H9 S5 C7 p/ F
  118. #endif
    6 E0 I: [0 g7 E7 o/ b' ]
  119. ( P7 A3 H) W4 O( V% U4 d: ?
  120.     ldmfd sp!, {r4}         ; pop new task cpsr to spsr
    , n2 Z5 d2 S& r1 ~& B: |- J7 Q
  121.     msr spsr_cxsf, r4
    7 W) P0 q/ `7 ~5 n9 N
  122.     ldmfd sp!, {r0-r12, lr, pc}^  ; pop new task r0-r12, lr & pc, copy spsr to cpsr3 J: W2 }4 m0 @+ T: K5 t2 e; U7 m1 C
  123. ; s" b6 I) H1 }& ?% x4 K& \" T

  124. - L3 `: F. N; U* c% ^/ V) q
  125.         #define Mode_USR        0x10' t/ c6 g8 T9 m0 Y
  126.         #define Mode_FIQ        0x114 F7 _& ]2 M  X+ ^
  127.         #define Mode_IRQ        0x12' @7 I; _0 ?. L3 {
  128.         #define Mode_SVC        0x13
    4 d( y. t) r+ K* a" t$ K, X- F
  129.         #define Mode_ABT        0x17
    0 ^  i4 M$ g4 J. o
  130.         #define Mode_UND        0x1B0 A% o0 p! O1 {$ c, R
  131.         #define Mode_SYS        0x1F5 @9 ~7 G1 j5 U

  132. % u7 {1 M& r9 D, [* X- X; N
  133.         #define I_Bit           0x80  g5 ]+ y/ v3 }2 S$ q
  134.         ; when I bit is set, IRQ is disabled
    # V+ y4 h1 E' O% ^& k3 s
  135.         #define        F_Bit           0x40* E2 b2 C" s4 E, `, ~
  136.         ; when F bit is set, FIQ is disabled
      [8 j, ]: z/ V4 R& E5 \

  137. 3 Z& n# ?9 e3 M, |! I6 _. T

  138. - M& M% f) i! @0 G% x) B
  139. ; void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);! c: j& u% E7 G

  140. ; P) ?2 I0 _- ]7 N# R3 ~& q  N/ v

  141. " A3 q# z$ Y% n& C
  142. & {4 O1 D$ w& v6 F, h1 E( S! p
  143. rt_hw_context_switch_interrupt:
    # u% R) g8 g6 o+ M6 E6 R
  144. #ifdef RT_USING_SMP( B8 ?) ~+ |. m$ |
  145.     ; r0 :irq_mod context0 e3 F' T3 P& y0 B5 c+ i
  146.     ; r1 :addr of from_thread's sp
    " J8 x5 L$ Q. T6 m0 ~
  147.     ; r2 :addr of to_thread's sp
    ! `! d. m" j0 H+ [7 j5 j
  148.     ; r3 :to_thread's tcb
    + O. P2 z" S7 C& Z7 D

  149. + F) N4 S) {& W" _5 P8 q- @

  150. ( d( O0 ~+ j- @
  151.     ; r0 point to {r0-r3} in stack
    4 {: Q; V' w. }1 S. M4 a1 M* j- W# R
  152.     push    {r1 - r3}: h9 b& U7 s* H- L
  153.     mov     r1, r0, T. m- h6 f4 x3 v0 A" A( |) e; ?, W% q
  154.     add     r0, r0, #4*4
    ! h  ~; b! w, N
  155.     ldmfd   r0!, {r4-r12,lr}; reload saved registers* y$ \4 `' }+ h8 u  }5 U5 q
  156.     mrs     r3,  spsr       ; get cpsr of interrupt thread2 Z5 B" l6 W9 x" b5 z$ Q9 B9 A
  157.     sub     r2,  lr, #4     ; save old task's pc to r28 |& R! C% n* `$ S: n
  158.     msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC$ i: ~4 M2 U. R" l  b4 h' f8 x
  159. 3 E) ]# L) e; T$ s8 x4 n
  160.     stmfd   sp!, {r2}       ; push old task's pc
    / [/ R' B8 E$ h# b1 F( p3 ^; u
  161.     stmfd   sp!, {r4-r12,lr}; push old task's lr,r12-r4
    ( J; Z# \9 @: D: Q- w, o' s
  162.     ldmfd   r1,  {r4-r7}    ; restore r0-r3 of the interrupt thread
    3 o% Q5 T$ f2 O& S# b
  163.     stmfd   sp!, {r4-r7}    ; push old task's r0-r38 i1 N3 d, _  Y
  164.     stmfd   sp!, {r3}       ; push old task's cpsr" {8 g$ q9 o. Q# L! s5 @& g. z; Y

  165. : M$ G, m, Q/ G7 _- k( `% U
  166. #ifdef RT_USING_LWP! }+ H: T+ Y6 J
  167.     stmfd sp, {r13,r14}^    ;push usr_sp usr_lr! `: X4 p- \* Q- {5 L5 @7 W
  168.     sub sp, #8
    5 |4 P2 r: h/ [" Q& T3 o  _
  169. #endif
    * C/ G/ M7 j5 ]5 K

  170. ! L$ F- ?( D& E2 n7 z
  171.     msr     cpsr_c, #I_Bit|F_Bit|Mode_IRQ+ b$ Y  `7 ]* _& j
  172.     pop     {r1 - r3}) m8 B+ F, ~& P/ q1 U
  173.     mov     sp, r0
    : p8 w% g8 M$ @: m$ u
  174.     msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC2 k4 z2 w9 M0 R) C
  175.     str     sp, [r1]8 N) D  H* N2 n: x- G
  176. # X" u. g( P3 Y1 j: m" N
  177.     ldr     sp, [r2]* W$ Y1 }4 h( T- [3 H0 u
  178.     mov     r0, r31 E7 N! x0 R. l' }; b1 E+ I
  179.     bl      rt_cpus_lock_status_restore
    4 W. d. R% J' i" S# D1 H& C* ~4 H
  180. ; I8 ]# F- \2 m6 }0 N* C$ T
  181. #ifdef RT_USING_LWP
    " G/ ]* c9 q5 l& z
  182.     ldmfd sp, {r13,r14}^  ;pop usr_sp usr_lr
    . X8 e7 C0 {; i7 h8 p9 L  T
  183.     add sp, #8
    2 `4 \; ~) r) x" Q# B
  184. #endif; q! Y7 u. q( p7 z7 f6 B7 z- q7 S
  185. 9 D: w1 ?! Z+ `* U
  186.     ldmfd   sp!, {r4}       ; pop new task's cpsr to spsr& @$ T: I1 M) a) o9 E' z% G
  187.     msr     spsr_cxsf, r4
    " S% v/ v+ K' g% `0 \
  188. 2 n% G; m' W7 a
  189.     ldmfd   sp!, {r0-r12,lr,pc}^ ; pop new task's r0-r12,lr & pc, copy spsr to cpsr. U+ Y% k; s- {' D4 W
  190. 3 g, a* p8 j: B( g# z$ [4 i3 T7 V
  191. #else* a6 r; r) N/ \
  192. ;/*RT_USING_SMP*/
    ! D& Z# \/ Y; N6 d
  193.     ldr r2, =rt_thread_switch_interrupt_flag4 W1 p, h' }- A
  194.     ldr r3, [r2]& y0 q/ {5 ?5 o, m$ F5 I
  195.     cmp r3, #1
    7 V8 w  X8 E2 X  ?  `1 K$ y: w) ?
  196.     beq _reswitch) U8 b" a6 r* s' p6 j8 ?4 w
  197.     ldr sp, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
    ( _" c3 F7 Q0 P& R% I' `" w. E2 o
  198.     mov r3, #1              ; set rt_thread_switch_interrupt_flag to 1
    # t+ x9 n$ T+ o1 g
  199.     str r0, [sp]! b! B# c- O6 W1 U6 y4 g
  200.     str r3, [r2]. [1 M' a$ ]& E# W, h
  201. _reswitch:
    9 k. Y% I4 w0 U' {# k
  202.     ldr r2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread3 l  U& P5 p& [9 j. ~8 F
  203.     str r1, [r2]9 p; h) O% v6 F8 x* [; x4 R1 [
  204.     bx  lr
    ' ~4 j; O0 V# u/ O6 {; h# f
  205. #endif( @- e7 M) h- ]
  206. ;/*RT_USING_SMP*/
    . o7 I+ I+ k* [, }  e- `; n( b7 b

  207. ; H" ?8 j" U( i4 f% }8 b  {
  208.         END7 G9 C: c; j1 Y8 v. e* L- Y
复制代码
QEMU_VEXPRESS_A9中的context.s是这样的
* w5 r. m) r+ R$ y5 s6 L
  1. #include "rtconfig.h"/ r# i9 g: E- e( M3 k) K
  2. .section .text, "ax"
    ' C, x) f. K2 |# A- M: ~* L2 h+ W- P
  3. , V# P3 a4 @. J
  4. #ifdef RT_USING_SMP
    4 O  z! I  p8 f( @2 ?6 i
  5. #define rt_hw_interrupt_disable rt_hw_local_irq_disable$ w3 N! D! L7 e6 N: T8 v
  6. #define rt_hw_interrupt_enable  rt_hw_local_irq_enable) X) D% _. t6 m6 N& c
  7. #endif8 ~. c: w6 r- X3 g9 S# Y7 m

  8. % I4 i$ A$ Z1 F$ S4 g3 P
  9. /*& W) f' N# J" o( X. n8 [
  10. * rt_base_t rt_hw_interrupt_disable();. `; i% s9 G1 P
  11. */
    3 F8 J4 o3 H; O& a9 e: b
  12. .globl rt_hw_interrupt_disable! D$ p, Q6 e: C) x6 l( a& e
  13. rt_hw_interrupt_disable:6 J) {" \! L; Z
  14.     mrs r0, cpsr
    % ~# ?* d' Y! s0 O, ~
  15.     cpsid i
    & t  y* {' J# h$ J3 i$ l8 |
  16.     bx  lr
    & b; b  s) n" b0 @7 A

  17. $ o0 o) A5 Q2 d+ ~' F$ n; K4 ]
  18. /*6 f+ M6 a, J1 K; N; X! V
  19. * void rt_hw_interrupt_enable(rt_base_t level);
      n1 s: m# R5 o: D0 M- L3 P
  20. */6 Q8 k% s0 d: K5 V% R; n/ O" e  ?
  21. .globl rt_hw_interrupt_enable8 L8 [- \# z: J
  22. rt_hw_interrupt_enable:" Z9 m6 w, Q1 [
  23.     msr cpsr, r0/ a/ M+ W$ E5 {. b
  24.     bx  lr
    , {- J! o9 {; d9 T4 `

  25. $ s" O6 S5 e4 R
  26. /*$ `3 d  {- q- J- v
  27. * void rt_hw_context_switch_to(rt_uint32 to);
    # k% v' Q& ~& h
  28. * r0 --> to7 |3 l- }4 m* \) F' ~- s5 P7 e
  29. */  _  W! f6 }) ?# a2 B" J, A
  30. .globl rt_hw_context_switch_to
    . Z( G2 e. }7 N
  31. rt_hw_context_switch_to:1 u# @. r  j. q$ j
  32.     ldr sp, [r0]            @ get new task stack pointer
    4 {0 J, Q* x0 `; l9 P3 f. B
  33. - _* l/ r, P. {7 N. B
  34. #ifdef RT_USING_SMP
    3 V6 q+ c7 b# B; X1 m
  35.     mov     r0, r1  {, r7 m0 x0 N9 D  T( a' w
  36.     bl      rt_cpus_lock_status_restore
    " Y1 D2 \4 F' W  _; Z
  37. #endif /*RT_USING_SMP*/( e3 p! U/ h' W) }9 o( W7 ^
  38. - f/ W' J( p: n0 o* v, ^
  39. #ifdef RT_USING_LWP
    $ N6 c2 x( C+ Y7 x! g+ T6 {) p
  40.     ldmfd sp, {r13, r14}^   @ pop usr_sp usr_lr
      C+ ?! `9 T! R7 Q7 ^% _# _
  41.     add sp, #8. @/ _4 ~! J( p' t- ?! x. M) P
  42. #endif
    3 s! K2 N2 _& v" Q

  43. / v, o4 R5 N( l: l5 {
  44.     ldmfd sp!, {r4}         @ pop new task spsr
    4 z: N+ I$ E& O: d( G: z" |
  45.     msr spsr_cxsf, r42 e* J7 c: W& q7 J* ^7 Z# Y! |

  46. ' N2 u: W4 ]) y2 C6 T0 j+ R
  47.     ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc. Q/ y6 v, q6 Z  [7 ^% I5 g) T
  48. * ^1 v; Y( m; ^- L' N5 [- O
  49. .section .bss.share.isr) Q! C4 ]6 G  T1 l
  50. _guest_switch_lvl:: }+ D, z  |8 u+ P! S; Z4 S9 b3 T
  51.     .word 0
    ; c$ C( G0 S# Y
  52. + m$ b- x4 b3 U& p* f' }6 r
  53. .section .text.isr, "ax"
    & c. T% P% [. r5 |+ I7 _
  54. /*8 E! i6 @# l3 g; B. o# e
  55. * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
    1 }( M6 U$ S. C2 d+ C
  56. * r0 --> from! z5 j  f6 X* c& T+ Z- q: y
  57. * r1 --> to
    % o# z4 V) V; y1 V' n2 x# t" E. r
  58. */
    + r; A9 N" ]% Z, V, e* N
  59. .globl rt_hw_context_switch
    & `+ F3 B+ c# w3 {( T; ?! M. v
  60. rt_hw_context_switch:
    ) P- k/ {& @: t# h2 K3 b, I& ?
  61.     stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)9 a3 ^3 V) |5 x/ Y% v+ _9 O* ^% b& {
  62.     stmfd   sp!, {r0-r12, lr}   @ push lr & register file- u. S) Z5 D  w( T: Q
  63. 2 G6 s, F# j3 M: e. Q+ W
  64.     mrs r4, cpsr
    " `$ w* ~4 \2 P- `+ p( t3 g) Z
  65.     tst lr, #0x01
    - V! H4 A5 s8 E, T* Q- ~% ^& @9 J
  66.     orrne r4, r4, #0x20     @ it's thumb code* a0 d4 z7 i: K7 g" e/ \
  67. & e* {8 K. @: p; H) Q! _
  68.     stmfd sp!, {r4}         @ push cpsr
    ; c7 k/ o1 U. L# m, R$ n

  69. 5 c* _$ }/ R$ b/ r2 S6 d
  70. #ifdef RT_USING_LWP8 l6 ]2 N7 ~9 i8 P# _1 \
  71.     stmfd sp, {r13, r14}^   @ push usr_sp usr_lr
      K6 ]* h1 k2 P1 S( f' J. D+ s2 e
  72.     sub sp, #8* O0 e. Q8 T7 D: J" o
  73. #endif$ R9 @2 f" V9 k" G1 A- _+ a
  74.   h$ H1 [! H1 Q# \7 T6 \
  75.     str sp, [r0]            @ store sp in preempted tasks TCB
    ) m2 A9 l. D+ `2 R
  76.     ldr sp, [r1]            @ get new task stack pointer4 n8 ~" k+ b" p) W7 e% k* y

  77. 0 c; K7 W6 k# R  G- a! b/ a2 f
  78. #ifdef RT_USING_SMP
    ; s9 a% P! ~5 ?: \' a; d
  79.     mov     r0, r2% a3 Z/ p1 N9 X" |
  80.     bl      rt_cpus_lock_status_restore9 n4 }% Z1 J5 N- }" E3 d- K- ]# |
  81. #endif /*RT_USING_SMP*/
    8 i0 \: T: w5 k1 @. `
  82. & D, X6 |; n; ~, d+ c7 E
  83. #ifdef RT_USING_LWP
    3 n* s4 v0 L  u
  84.     ldmfd sp, {r13, r14}^   @ pop usr_sp usr_lr9 R0 O. w9 Z+ n, _8 K8 u
  85.     add sp, #8
    . r* a/ l+ K! y9 u# B+ ]
  86. #endif
    / `9 Y4 t/ j1 z) b3 j- V

  87. , w; }8 Z; t4 V+ X* c
  88.     ldmfd sp!, {r4}         @ pop new task cpsr to spsr* |$ n+ n% h: N
  89.     msr spsr_cxsf, r4' X/ b& s: ?) G
  90.     ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr2 I" \% F; \6 K8 K/ t  G. f& C

  91. ( S$ W3 _! d' V3 A1 I  x8 x
  92. /*
    & r/ s0 j/ t( E7 b  x) L3 B- i1 @
  93. * void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);2 ?6 m) _2 }8 p/ w' N4 ]
  94. */
    7 D$ |' ]2 `2 k! T9 y) |
  95. .equ Mode_USR,        0x10
    " K5 T' W# R$ x$ D! Q3 G% n
  96. .equ Mode_FIQ,        0x11; `; t3 n  S2 W8 M7 w  y
  97. .equ Mode_IRQ,        0x12. }: Q% `3 ]+ R2 u- n
  98. .equ Mode_SVC,        0x137 \* ]# l3 V/ S: `9 m
  99. .equ Mode_ABT,        0x176 z  m: h* j. W% u! G+ Q6 q% D
  100. .equ Mode_UND,        0x1B. P' r* Q9 \6 I+ C3 x6 p( X6 M3 T
  101. .equ Mode_SYS,        0x1F
    * s$ m0 r" @% O& N6 c

  102. % b# }. M  L# H1 @% [6 x
  103. .equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled" V: ~/ s# K1 L$ B, a+ K+ w1 L
  104. .equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
    5 f4 S* U" a* D2 M) ]% \' @  p

  105. ! T* z, F1 `) D) F
  106. .globl rt_thread_switch_interrupt_flag' J2 s2 o! ~4 A/ g# L6 O1 s5 j) d
  107. .globl rt_interrupt_from_thread
    4 X7 i  k2 Y& F1 m' |/ j0 F" d0 u
  108. .globl rt_interrupt_to_thread
    6 |$ s+ ~4 F) m2 X% ^/ M. b
  109. .globl rt_hw_context_switch_interrupt3 k' T/ L. v  U8 A( M; L3 {
  110. rt_hw_context_switch_interrupt:
    % q5 R1 [. L- Y2 Z2 Q: N  O
  111. #ifdef RT_USING_SMP# @. n  t% @6 O
  112.     /* r0 :irq_mod context( m' f1 t) F8 f$ k+ p* u- M
  113.      * r1 :addr of from_thread's sp5 N+ w' n8 E# I" H
  114.      * r2 :addr of to_thread's sp  F1 F: `6 b4 \7 p* W, K* m! _
  115.      * r3 :to_thread's tcb& ^, W' W6 z  @( D2 {" e
  116.      */6 z3 N6 C' u; U; F2 t+ |: ?9 J3 v

  117. # ^# D$ p: `4 d1 A7 F
  118.     @ r0 point to {r0-r3} in stack1 c3 Q7 x0 H* N( w
  119.     push    {r1 - r3}4 f6 N  a7 ?" p9 _7 N5 b
  120.     mov     r1, r0  _! R- b8 r* x
  121.     add     r0, r0, #4*40 a+ s- T* S  e) l
  122.     ldmfd   r0!, {r4-r12,lr}@ reload saved registers7 X5 n( P7 w3 Y1 M$ ?- n
  123.     mrs     r3,  spsr       @ get cpsr of interrupt thread0 k9 Y' u. T. t! m1 O9 B
  124.     sub     r2,  lr, #4     @ save old task's pc to r2/ `# A0 {: e+ A( [  @( d# v
  125.     msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
    ! N( }% ^5 _$ b( x0 V5 C
  126. ! V  v% T# j# _0 b
  127.     stmfd   sp!, {r2}       @ push old task's pc  ~$ R; M8 l  N# _  f
  128.     stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
    8 S0 V* L; l$ d7 |& c* _7 U
  129.     ldmfd   r1,  {r4-r7}    @ restore r0-r3 of the interrupt thread  o) n8 s/ b% ~# Z% Z% L. E
  130.     stmfd   sp!, {r4-r7}    @ push old task's r0-r3
    $ c  v6 S9 s  J% Z. u
  131.     stmfd   sp!, {r3}       @ push old task's cpsr" o/ N) M9 u5 c( k  h/ |
  132. 4 W& T. G/ m& s7 e' R
  133. #ifdef RT_USING_LWP
    2 W# i( m! P; H" L0 Y1 U9 Y6 D
  134.     stmfd sp, {r13,r14}^    @push usr_sp usr_lr
    5 U( d+ v3 ?, r; q
  135.     sub sp, #8" E  x6 {" I3 @- H- S$ W
  136. #endif' g! f, u! _3 J+ r, a4 ^/ c

  137.   `2 ~* }* c7 P- u
  138.     msr     cpsr_c, #I_Bit|F_Bit|Mode_IRQ5 x& u2 {/ l* K( G
  139.     pop     {r1 - r3}: \3 _: B" w& ]2 n
  140.     mov     sp, r02 [! L7 q7 Y" Q* r0 S5 K
  141.     msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC0 r/ Z) m# s0 ~0 s2 w2 X
  142.     str     sp, [r1]( P- x- o" n+ f3 k5 k

  143.   Q) p- \1 e2 ?( \# u2 \- h/ [2 S0 Q
  144.     ldr     sp, [r2]
    # N& n  F2 Q/ }; \) r" }/ @+ e/ `9 C
  145.     mov     r0, r3
    * F3 f3 l9 V6 C  \! e( J$ d- s3 w' n
  146.     bl      rt_cpus_lock_status_restore
    7 Z6 @. u4 C8 i

  147. * c5 J: I0 p7 r
  148. #ifdef RT_USING_LWP& C7 r7 E% D1 E5 p
  149.     ldmfd sp, {r13,r14}^  @pop usr_sp usr_lr
    ) z* ^" }9 b8 v8 b3 j. U( A, D
  150.     add sp, #82 s# B! S. A+ O, W0 A7 |" C
  151. #endif
    1 }! P: R2 X  H8 ^% y( L$ U
  152. ( j- g$ i6 b: y( E1 G: Q  j
  153.     ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
    7 @9 P) K, v6 O" J
  154.     msr     spsr_cxsf, r4
    * x" A. w' g& d& ]% G2 r
  155. ! H, T( w2 T+ X, e" i
  156.     ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr! j: _6 s  e- d2 B; ~
  157. , ?1 p. M# P% W) w( K" R/ V8 Q* n
  158. #else /*RT_USING_SMP*/1 M. Q9 `. W( c6 b; d. j
  159.     ldr r2, =rt_thread_switch_interrupt_flag
    0 e' o/ O) a( b% ^" M0 h+ g9 }$ t
  160.     ldr r3, [r2]
    . d2 y9 l! k" V$ Z
  161.     cmp r3, #19 W9 k- Y5 z/ r! t  p9 m
  162.     beq _reswitch
      q9 N+ e( q. }+ I1 O
  163.     ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
    6 q7 R5 w% i2 r1 H' z; C; w7 ^
  164.     mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
    9 f& ~+ D+ M2 @- p4 D$ z- h
  165.     str r0, [ip]9 X) k+ A# r5 _7 C! @
  166.     str r3, [r2]9 j# k0 ~5 R5 o6 F
  167. _reswitch:" y2 m( w( t" x# u% t4 R' [
  168.     ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
    * }' g+ ?6 K$ Y2 U, V5 q9 _9 f
  169.     str r1, [r2]
    9 z3 M" Z+ s4 o8 m4 w/ a
  170.     bx  lr1 }% e) F5 P3 o! X& @& j( U+ D+ b
  171. #endif /*RT_USING_SMP*/
复制代码
弄了好几天一直卡在这,求大神指点( [3 d, H6 D2 u* L& c

- i1 |+ _& d+ l  ~7 W. C( d3 |% A- X9 j# Q" j4 i5 h* l
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发表于 2019-4-24 12:31:39 | 显示全部楼层
多核版本?移植部分都弄好了?
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发表于 2019-4-24 13:08:24 | 显示全部楼层
bernard 发表于 2019-4-24 12:31
' @8 y: x4 {% E& X! \1 Y3 b: n" U多核版本?移植部分都弄好了?

( x' l8 h' {* Z' \( o 移植肯定弄好了 ,否则IAR编译也不能通过,原来是在不带系统的时候,改好了底层驱动,后来一点道移植到rt_thread上的,现在卡在这略尴尬,原来是我向老板推荐的这个系统,要是做不出来就坑了8 t% Z  r2 D' j4 l
   beq _reswitch
2 n7 F7 M* V' I7 W0 v" `& T, J6 Z    ldr ip, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
$ {6 k  z' Y; B, P: }# {    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1  _/ Q/ _, V: p& T5 E5 N
    str r0, [ip]
8 M7 y) L2 p- ]  [    str r3, [r2]
# [7 @% Q2 i+ P% e' y( d! t上面这段汇编里边有个困惑的if  ,为什么会用到ip寄存器,是不是写错了  arm里边没有ip寄存器吧
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发表于 2019-4-24 13:10:44 | 显示全部楼层
bernard 发表于 2019-4-24 12:31* `/ {# r, ~* _, R3 T; d4 [
多核版本?移植部分都弄好了?

9 K# K$ K; D' A* `- y8 h! S3 D& x" B/ U原来在不带系统的情况下,就是基于imx给出SDK,自己实现了SPI通信,还有一些定时模块,现在要充分释放这块单核1GHz的四核板性难,必须找个开源的支持SMP的多核系统
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发表于 2019-4-24 13:12:18 | 显示全部楼层
hwx628 发表于 2019-4-24 13:08/ @- G& B" X0 [: s; U
移植肯定弄好了 ,否则IAR编译也不能通过,原来是在不带系统的时候,改好了底层驱动,后来一点道移植到r ...

8 f# R- b/ \& r# ~4 L% b/ O" \* Q我把ip改成了SP才编译通过的,但是两个含义完全不一样,这个文件中在SMP模式下,就用的sp,为什么单核就突然冒出了ip
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发表于 2019-4-24 15:18:12 | 显示全部楼层
那你先用gcc跑通,跑起来吧
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发表于 2019-4-24 15:58:57 | 显示全部楼层
hwx628 发表于 2019-4-24 13:08
; ~! O' T5 I& k: ~! d移植肯定弄好了 ,否则IAR编译也不能通过,原来是在不带系统的时候,改好了底层驱动,后来一点道移植到r ...
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移植做好不等于编译做好,这个是两个概念。需要底层的代码,汇编代码都处理好。多核部分,还和多核的启动方式也相关
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